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SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 1 version 1.6 SN8P1917 user?s manual specification version 1.6 s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without further notice to any products herein to improve reliability, function or desig n. sonix does not assume any liability arising out of the application or use of an y product or circuit described her ein; neither does it convey a ny license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in systems inten ded, for surgical implant into the body, or other applications intended to suppor t or sustain life, or for any other application in which the fai lure of the sonix product could create a situation where personal injury or death may occu r. should buyer purchase or use sonix products for any such uni ntended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subs idiaries, affiliates and distri butors harmless against all claims, cost, damages, and expenses, and re asonable attorney fees arising out of, dire ctly or indirectly, any claim of pers onal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 2 version 1.6 amendent history version date description ver 0.1 aug. 2005 first issue. ver 0.2 sep. 2005 1. add lcd bias register 2. chapter 10 sample modified 3. change fds setting 4. change programming pin of p1.1/p1.2 5. 10.4.3 note error. 6. adc clock rater change 7. add brown-out circuit. ver. 0.3 nov. 2005 1. for new ve rsion chip (b) application 2. ampcks selection update 3. adcm register update for rvs and irvs ver. 0.4 nov. 2005 1. add adc current. 2. modify topr value. ver.0.5 dec. 2005 1. modify 8p1917_prev04 brown-out reset description. 2. modify electrical characteristic. 3. remove calibration function. ver.0.6 jan. 2006 1. change x+/x- capacitor to 0.01uf 2. internal reference voltage depend on ave+ 3. chopper frequency suggestion value is 2k 4. remove p1w, p0ur 5. add v1/v2 description. 6. change adenb to adcenb 7. change ave+, avddr characteristic data. ver.1.0 apr. 2006 1. add instruction set table 2. remove irefenb bit 3. ram data-retention spec. is min. 4. remove migration table of pgia temp . resistance and adc work in slow mode 5. avddcp capacitor is 10 uf of pin description 6. remove p4con register 7. correct irvs and adcm setting of reference table 8. add vss pin (pin40) into program table ver.1.1 may. 2006 1. temp sensor ch. should be 101 not 100. (on graphic) 2. add vlcd pin connect to vdd when otp programming 3. avddcp /acm capacitor connection on 5v and 3v 4. update application circuit. ver.1.2 sep. 2006 1. modified cpcks/ampcks/adcks as write mode register 2. limit the adc linear range as 28125 in adc chapter and elec. char. 3. add ts-temperature sensor elec. spec. 4. change cpcks as 15.6k 5. modified acm elec. spec. 6. modified pgia offset of elec. spec. ver.1.3 dec. 2006 1. modified p00g[1:0] function description. ver.1.4 jan. 2007 1. add marking definition. 2. modify electrical characteristic. ver.1.5 apr. 2007 1. add lcd circuit. ver 1.6 sep. 2007 1. remove dip48 package.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 3 version 1.6 table of content amendent history........................................................................................................................ ........ 2 1 1 1 product overview............................................................................................................... .......... 7 1.1 selection table......................................................................................................................... 7 1.2 migration table........................................................................................................................ 7 1.3 features ................................................................................................................... ..................... 8 1.4 system block diagram .......................................................................................................... 9 1.5 pin assignment ..................................................................................................................... .... 10 1.6 pin descriptions................................................................................................................... .... 11 1.7 pin circuit diagrams............................................................................................................. 12 2 2 2 central processor unit (cpu) .............................................................................................. 13 2.1 memory map............................................................................................................................ ... 13 2.1.1 program memory (rom) ................................................................................................. 13 2.1.2 code option table ........................................................................................................... 22 2.1.3 data memory (ram)........................................................................................................... 23 2.1.4 system register................................................................................................................ .24 2.2 addressing mode .................................................................................................................... 34 2.2.1 immediate addressing mode....................................................................................... 34 2.2.2 directly addressing mode .......................................................................................... 34 2.2.3 indirectly addressing mode ...................................................................................... 34 2.3 stack operation...................................................................................................................... 35 2.3.1 overview ....................................................................................................................... ....... 35 2.3.2 stack registers ................................................................................................................ .36 2.3.3 stack operation example............................................................................................. 37 3 3 3 reset .......................................................................................................................... ........................... 38 3.1 overview................................................................................................................... .................. 38 3.2 power on reset......................................................................................................................... 3 9 3.3 watchdog reset...................................................................................................................... 39 3.4 brown out reset ..................................................................................................................... 40 3.4.1 brown out description ................................................................................................. 40 3.4.2 the system operating voltage decsription........................................................ 41 3.4.3 brown out reset improvement.................................................................................. 41 3.5 external reset ........................................................................................................................ 43 3.6 external reset circuit ....................................................................................................... 43 3.6.1 simply rc reset circuit ........................................................................................................ ... 43 3.6.2 diode & rc reset circuit ....................................................................................................... .44
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 4 version 1.6 3.6.3 zener diode reset circuit ...................................................................................................... .. 44 3.6.4 voltage bias reset circuit..................................................................................................... ... 45 3.6.5 external reset ic.............................................................................................................. ........ 45 4 4 4 system clock ................................................................................................................... ............... 46 4.1 overview................................................................................................................... .................. 46 4.2 clock block diagram .......................................................................................................... 46 4.3 oscm register ....................................................................................................................... .... 47 4.4 system high clock ................................................................................................................. 48 4.4.1 internal high rc............................................................................................................... 48 4.4.2 external high clock...................................................................................................... 48 4.5 system low clock .................................................................................................................. 50 4.5.1 system clock measurement ........................................................................................ 51 5 5 5 system operation mode .......................................................................................................... .52 5.1 overview................................................................................................................... .................. 52 5.2 system mode switching example ................................................................................... 53 5.3 wakeup ..................................................................................................................... .................... 54 5.3.1 overview ....................................................................................................................... ....... 54 5.3.2 wakeup time.................................................................................................................... .... 54 6 6 6 interrupt...................................................................................................................... ..................... 55 6.1 overview................................................................................................................... .................. 55 6.2 inten interrupt enable register................................................................................... 55 6.3 intrq interrupt request register ................................................................................ 56 6.4 gie global interrupt operation .................................................................................... 56 6.5 push, pop routine .................................................................................................................... 57 6.6 int0 (p0.0) interrupt operation......................................................................................... 58 6.7 t0 interrupt operation ....................................................................................................... 59 6.8 multi-interrupt operation............................................................................................... 60 7 7 7 i/o port ....................................................................................................................... ......................... 61 7.1 i/o port mode ........................................................................................................................... .. 61 7.2 i/o pull up register ................................................................................................................ 62 7.3 i/o port data register .......................................................................................................... 63 8 8 8 timers ......................................................................................................................... ......................... 64 8.1 watchdog timer (wdt) ......................................................................................................... 64 8.2 timer 0 (t0) ........................................................................................................................... ........ 66 8.2.1 overview ....................................................................................................................... ....... 66 8.2.2 t0m mode register........................................................................................................... 66
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 5 version 1.6 8.2.3 t0c counting register................................................................................................... 67 8.2.4 t0 timer operation sequence ..................................................................................... 68 9 9 9 lcd driver ..................................................................................................................... .................... 69 9.1 lcdm1 register....................................................................................................................... .. 69 9.2 lcd timing ......................................................................................................................... .......... 70 9.3 lcd ram location ................................................................................................................... 72 9.4 lcd c ircuit ............................................................................................................................... ..... 73 1 1 1 0 0 0 charge-pump, pgia and adc ................................................................................................ 75 10.1 overview.................................................................................................................. ................... 75 10.2 analog input.......................................................................................................................... ... 75 10.3 v oltage c harge p ump / r egulator (cpr) ................................................................................. 76 10.3.1 cpm-charge pump mode register.......................................................................................... 76 10.3.2 cpcks-charge pump clock register ..................................................................................... 78 10.4 pgia -p rogrammable g ain i nstrumentation a mplifier ......................................................... 80 10.4.1 ampm- amplifier mode register............................................................................................. 80 10.4.2 ampcks- pgia clock selection ................................................................................... 81 10.4.3 ampchs-pgia channel selection ............................................................................... 82 10.4.4 temperature sensor (ts)........................................................................................................ .. 83 10.5 16-b it adc ............................................................................................................................ .......... 86 10.5.1 adcm- adc mode register .................................................................................................... 86 10.5.2 adcks- adc clock register .................................................................................................. 89 10.5.3 adcdl- adc low-byte data register ................................................................................... 90 10.5.4 adcdh- adc high-byte data register ................................................................................. 90 10.5.5 dfm-adc digital filter mode register ................................................................................. 91 10.5.6 lbtm : low battery detect register ....................................................................................... 94 10.5.7 analog setting and application................................................................................................ 9 5 1 1 1 1 1 1 application circuit............................................................................................................ .... 97 11.1 s cale (l oad c ell ) a pplication c ircuit ..................................................................................... 97 11.2 t hermometer a pplication c ircuit ............................................................................................. 98 1 1 1 2 2 2 instruction set table.......................................................................................................... .99 1 1 1 3 3 3 development tools .............................................................................................................. 100 13.1 d evelopment t ool v ersion ....................................................................................................... 100 13.1.1 ice (in circuit emulation) ..................................................................................................... . 100 13.1.2 otp writer ..................................................................................................................... ........ 100 13.1.3 ide (integrated development environment) ......................................................................... 100 13.2 otp p rogramming p in to t ransition b oard m apping ........................................................... 101
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 6 version 1.6 13.2.1 the pin assignment of easy and mp ez writer transition board socket:.............................. 101 13.2.2 the pin assignment of writer v3.0 transition board socket:.................................................. 101 13.2.3 SN8P1917 series programming pin mapping: ..................................................................... 102 1 1 1 4 4 4 electrical characteristic ............................................................................................ 103 14.1 absolute maximum rating .............................................................................................. 103 14.2 electrical characteristic............................................................................................. 103 1 1 1 5 5 5 package information ......................................................................................................... 106 15.1 ssop 48 pin............................................................................................................................ ....... 106 1 1 1 6 6 6 marking definition............................................................................................................. .. 107 16.1 introduction .............................................................................................................. ............ 107 16.2 marking indetification system.................................................................................... 107 16.3 marking example ................................................................................................................. 108 16.4 datecode system .................................................................................................................. 108
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 7 version 1.6 1 1 1 product overview 1.1 selection table timer chip rom ram stack lcd t0 tc0 tc1 i/o adc pwm buzzer sio wakeup pin no. package sn8p1907 2k*16 128*8 8 4*12 v - - 11 16-bit - - 5 ssop48 SN8P1917 2k*16 128*8 8 4*12 v - - 13 16-bit - - 5 ssop48 table 1-1 selection table of SN8P1917 1.2 migration table migration SN8P1917 series to sn8p1907 series item SN8P1917 sn8p1907 pgia gain setting 1x, 12.5x, 50x, 100x, 200x 1x, 16x, 32x, 64x, 128x pgia temperature drift good no good ave+ voltage 3.0v or 1.5v 3.0v only adc reference voltage v(r+, r-) 0.8v or 0.4v 0.8v only battery detect method by comparator or by adc by adc only temperature sensor build in external acm (1.2v) voltage not change with sink current change with sink current charge pump clock frequency (cpcks) 4-bit selection 2-bit selection chopper clock frequency (ampcks) 3-bit selection 2-bit selection charge pump regulator working in slow mode yes no operating current consumption less more slow mode current consumption less more lcd bias voltage 1/3 or 1/2 bias 1/2 bias only internal 16m rc oscillator yes no p2 [1:0] i/o available when fosc=ihrc no otp programming method serial method parallel method table 1-2 SN8P1917 migration table
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 8 version 1.6 1.3 features memory configuration two interrupt sources otp rom size: 2k * 16 bits one internal interrupts: t0 ram size: 128 * 8 bits (bank 0) one external interrupts: int0 8-levels stack buffer single power supply: 2.4v ~5.5v lcd ram size: 4*12 bits on-chip watchdog timer i/o pin configuration on-chip charge-pump re g ulator with 3.8v volta g e output and 10ma driven current. input only: p0, p4 on chip regulator with 3.0v/1.5v output voltage bi-directional: p1, p2 on-chip 1.2v band gap reference for batter y monitor. output only: p5 on chip voltage comparator. wakeup: p0, p1 build in adc reference voltage v(r+,r- ) =0.8v or 0.4v. pull-up resisters: p0, p1, p2, p4 build in temperature sensor. external interrupt: p0 powerful instructions lcd driver: four clocks per instruction cy cle 1/3 or 1/2 bias voltage. all instructions are one word length 4 common * 12 segment most of instructions are 1 cycle only. maximum instructio n cycle is ?2?. dual clock system offers four operating modes jmp instruction jumps to all rom area. external high clock: rc type up to 10 mhz all rom area look-up table function (movc) external high clock: crystal type up to 8 mhz normal mode: both high and low clock active. programmable gain instrumentation amplifier slow mode: low clock only. gain option: 1x/12.5x/50x/100x/200x sleep mode: both high and low clock stop. build in pgia temperature compensation resistance package 16-bit delta-sigma adc with 14-bit noise free ssop48 two adc channel configuration: one fully differential channel two single channels
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 9 version 1.6 1.4 system block diagram figure 1-1 simplified system block diagram interrupt control external high osc. acc internal low rc internal high rc timing generator ram system registers lvd (low voltage detector) watchdog timer pgia comparator timer & counter p0 p5 p4 16-bit adc charge pump regulator alu pc flags ir otp rom avddcp ai+/ai- avddr ave+ lbtin2/1 r+/r- internal reference internal adc channel for battery detect p1 p2
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 10 version 1.6 1.5 pin assignment seg4 1 48 seg5 seg3 2 47 seg6 seg2 3 46 seg7 seg1 4 45 seg8 seg0 5 44 seg9 com3 6 43 seg10 com2 7 42 seg11 com1 8 41 vpp/rst com0 9 40 vss vlcd 10 39 p5.2 r+ 11 38 p5.1 r- 12 37 p5.0 x+ 13 36 p4.2/lbtin2 x- 14 35 p4.1/lbtin1 ai+ 15 34 p4.0 ai- 16 33 p1.3 avss 17 32 p1.2 acm 18 31 p1.1 addr 19 30 p1.0 ave+ 20 29 p0.0/int0 avddcp 21 28 vdd c+ 22 27 xout/p2.1 vdd 23 26 xin/p2.0 c- 24 25 vss
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 11 version 1.6 1.6 pin descriptions pin name type description vdd, vss, avss p power supply input pins for digital / analog circuit. vlcd p lcd power supply input avddr p regulator power output pin, voltage=3.8v. ave+ p regulator output =3.0v or 1.5v fo r sensor. maximum output current=10 ma acm p band gap voltage output =1.2v avddcp p charge pump voltage output. ( connect a 10uf or higher capacitor to ground) r+ ai positive reference input r- ai negative reference input x+ ai positive adc differential input, a 0.1uf capacitor connect to pin x- x- ai negative adc differential input ai+ ai positive analog input channel ai- ai negative analog input channel c+ a positive capacitor terminal for charge pump regulator c- a negative capacitor terminal for charge pump regulator vpp/ rst p, i otp rom programming pin. system reset input pin. schmitt trigger struct ure, active ?low?, normal stay to ?high?. xin, xout i, o external high clock oscillator pins. rc mode from xin. p0.0 / int0 i port 0.0 and shared with int0 trig ger pin (schmitt trigger) / built-in pull-up resisters. p1 [3:0] i/o port 1.0~port 1.3 bi-direction pins / wakeup pins/ built-in pull-up resisters. p2 [1:0] i/o port 2.0~port 2.1 bi-direction pins / built-in pull-up resisters. shared with xin/xout p4 [2:0] i port 4.0~port 4.2 input pins/ built-in pull-up resisters p5 [2:0] o port 5.0~port 5.2 output pins lbtin1/2 i i low battery detect i nput pins shared with p4.1, p4.2 com [3:0] o com0~com3 lcd driver common port seg0 ~ seg11 o lcd driver segment pins.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 12 version 1.6 1.7 pin circuit diagrams port 0, port 4structure: port 5 structure: port1 structure: port2 structure: pull-up pin pnur input bus pin output latch output bus pull-up pin output latch pnm, pnur input bus pnm output bus oscillator code option int. osc. pull-up pin output latch pnm, pnur input bus pnm output bus
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 13 version 1.6 2 2 2 central processor unit (cpu) 2.1 memory map 2.1.1 program memory (rom) ) 2k words rom rom 0000h reset vector user reset vector 0001h jump to user start address 0002h jump to user start address 0003h general purpose area jump to user start address 0004h 0005h 0006h 0007h reserved 0008h interrupt vector user interrupt vector 0009h user program . . 000fh 0010h 0011h . . 7feh general purpose area end of user program 7ffh reserved
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 14 version 1.6 2.1.1.1 reset vector (0000h) a one-word vector address area is used to execute system reset. ) power on reset ) watchdog rese ) external reset after power on reset, external reset or watchdog timer over flow reset, then the chip will restart the program from address 0000h and all system re gisters will be set as default values. the following example shows the way to define the reset vector in the program memory. ? example: defining reset vector org 0 ; 0000h jmp start ; jump to user program address. ? org 10h start: ; 0010h, the head of user program. ? ; user program ? endp ; end of program
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 15 version 1.6 2.1.1.2 interrupt vector (0008h) a 1-word vector address area is used to execute interr upt request. if any interrupt se rvice executes, the program counter (pc) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. users have to define the interr upt vector. the following example shows the wa y to define the interrupt vector in the program memory. ? note: users have to save and load acc and pflag register by program as interrupt occurrence. ? example: defining interrupt vector. the in terrupt service routine is following org 8. .data accbuf ds 1 ; define accbuf for store acc data. pflagbuf ds 1 ; define pflagbuf for store pflag data. .code org 0 ; 0000h jmp start ; jump to user program address. ? org 8 ; interrupt vector. b0xch a, accbuf ; save acc in a buffer. b0mov a, pflag b0mov pflagbuf, a ; save pflag register in a buffer. ? ? b0mov a, pflagbuf b0mov pflag, a ; restore pflag register from buffer. b0xch a, accbuf ; restore acc from buffer. reti ; end of interrupt service routine ? start: ; the head of user program. ? ; user program ? jmp start ; end of user program ? endp ; end of program
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 16 version 1.6 ? example: defining interrupt vector. the interru pt service routine is following user program. .data accbuf ds 1 ; define accbuf for store acc data. pflagbuf ds 1 ; define pflagbuf for store pflag data. .code org 0 ; 0000h jmp start ; jump to user program address. ? org 8 ; interrupt vector. jmp my_irq ; 0008h, jump to interrupt service routine address. org 10h start: ; 0010h, the head of user program. ? ; user program. ? ? jmp start ; end of user program. ? my_irq: ;the head of interrupt service routine. b0xch a, accbuf ; save acc in a buffer. b0mov a, pflag b0mov pflagbuf, a ; save pflag register in a buffer. ? ? b0mov a, pflagbuf b0mov pflag, a ; restore pflag register from buffer. b0xch a, accbuf ; restore acc from buffer. reti ; end of interrupt service routine. ? endp ; end of program. ? note: it is easy to understand the rules of sonix program from demo programs given above. these points are as following: 1. the address 0000h is a ?jmp? instruction to make the program starts from the beginning. 2. the address 0008h is interrupt vector. 3. user?s program is a loop routine for main purpose application.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 17 version 1.6 2.1.1.3 look-up table description in the rom?s data lookup function, y register is pointed to middle byte address (bit 8~bit 15) and z register is pointed to low byte address (bit 0~bit 7) of rom. after movc instruction executed, t he low-byte data will be stored in acc and high-byte data stored in r register. ? example: to look up the rom data located ?table1?. b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low address. movc ; to lookup data, r = 00h, acc = 35h ; increment the index address for next address. incms z ; z+1 jmp @f ; z is not overflow. incms y ; z overflow (ffh ? 00), ? y=y+1 nop ; ; @@: movc ; to lookup data, r = 51h, acc = 05h. ? ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ? ? note: the y register will not increase automatically wh en z register crosses boundary from 0xff to 0x00. therefore, user must take care such situation to avoid look-up table errors. if z register overflows, y register must be added one. the following inc_yz macro shows a simple method to process y and z registers automatically. ? example: inc_yz macro. inc_yz macro incms z ; z+1 jmp @f ; not overflow incms y ; y+1 nop ; not overflow @@: endm
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 18 version 1.6 ? example: modify above exam ple by ?inc_yz? macro. b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low address. movc ; to lookup data, r = 00h, acc = 35h inc_yz ; increment the index address for next address. ; @@: movc ; to lookup data, r = 51h, acc = 05h. ? ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ? the other example of look-up table is to add y or z index r egister by accumulator. please be careful if ?carry? happen. ? example: increase y and z register by b0add/add instruction. b0mov y, #table1$m ; to set lookup table?s middle address. b0mov z, #table1$l ; to set lookup table?s low address. b0mov a, buf ; z = z + buf. b0add z, a b0bts1 fc ; check the carry flag. jmp getdata ; fc = 0 incms y ; fc = 1. y+1. nop getdata: ; movc ; to lookup data. if buf = 0, data is 0x0035 ; if buf = 1, data is 0x5105 ; if buf = 2, data is 0x2012 ? table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ?
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 19 version 1.6 2.1.1.4 jump table description the jump table operation is one of multi-address jumpin g function. add low-byte program counter (pcl) and acc value to get one new pcl. the new program counter (pc) points to a series jump instructions as a listing table. it is easy to make a multi-jump program depends on the value of the accumulator (a). when carry flag occurs after ex ecuting of ?add pcl, a?, it will not affect p ch register. users have to check if the jump table leaps over the rom page boundary or the listing file generated by sonix assembly software. if the jump table leaps over the rom page boundary (e.g. from xxffh to xx0 0h), move the jump table to the top of next program memory page (xx00h). here one page mean 256 words. ? note: program counter can?t carry from pcl to pch when pcl is overflow after executin g addition instruction. ? example: jump table. org 0x0100 ; the jump table is from the head of the rom boundary b0add pcl, a ; pcl = pcl + acc, the pch can?t be changed. jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point in following example, the jump table starts at 0x00fd. w hen execute b0add pcl, a. if acc = 0 or 1, the jump table points to the right address. if the acc is larger then 1 will cause error be cause pch doesn't incr ease one automatically. we can see the pcl = 0 when acc = 2 but the pch still keep in 0. the progra m counter (pc) will point to a wrong address 0x0000 and crash system ope ration. it is important to check whethe r the jump table crosses over the boundary (xxffh to xx00h). a good coding style is to put t he jump table at the start of rom boundary (e.g. 0100h). ? example: if ?jump table? crosses over rom boundary will cause errors. rom address ? ? ? 0x00fd b0add pcl, a ; pcl = pcl + ac c, the pch can?t be changed. 0x00fe jmp a0point ; acc = 0 0x00ff jmp a1point ; acc = 1 0x0100 jmp a2point ; acc = 2 ? jump table cross boundary here 0x0101 jmp a3point ; acc = 3 ? ?
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 20 version 1.6 sonix provides a macro for safe jump table function. th is macro will check the rom boundary and move the jump table to the right position automatically. the side e ffect of this macro maybe wastes some rom size. ? example: if ?jump table? crosses over rom boundary will cause errors. @jmp_a macro val if (($+1) !& 0xff00) !!= (($+(val)) !& 0xff00) jmp ($ | 0xff) org ($ | 0xff) endif add pcl, a endm ? note: ?val? is the number of the jump table listing number. ? example: ?@jmp_a? application in sonix macro file called ?macro3.h?. b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point jmp a4point ; acc = 4, jump to a4point if the jump table position is across a rom boundary (0x00ff~ 0x0100), the ?@jmp_a? macro will adjust the jump table routine begin from next ram boundary (0x0100). ? example: ?@jmp_a? operation. ; before compiling program. rom address b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. 0x00fd jmp a0point ; acc = 0, jump to a0point 0x00fe jmp a1point ; acc = 1, jump to a1point 0x00ff jmp a2point ; acc = 2, jump to a2point 0x0100 jmp a3point ; acc = 3, jump to a3point 0x0101 jmp a4point ; acc = 4, jump to a4point ; after compiling program. rom address b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. 0x0100 jmp a0point ; acc = 0, jump to a0point 0x0101 jmp a1point ; acc = 1, jump to a1point 0x0102 jmp a2point ; acc = 2, jump to a2point 0x0103 jmp a3point ; acc = 3, jump to a3point 0x0104 jmp a4point ; acc = 4, jump to a4point
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 21 version 1.6 2.1.1.5 checksum calculation the last rom address are reserved area. user should avoi d these addresses (last address) when calculate the checksum value. ? example: the demo program shows how to calculated checksum from 00h to the end of user?s code. mov a,#end_user_code$l b0mov end_addr1, a ; save low end address to end_addr1 mov a,#end_user_code$m b0mov end_addr2, a ; save middle end address to end_addr2 clr y ; set y to 00h clr z ; set z to 00h @@: movc b0bset fc ; clear c flag add data1, a ; add a to data1 mov a, r adc data2, a ; add r to data2 jmp end_check ; check if the yz address = the end of code aaa: incms z ; z=z+1 jmp @b ; if z != 00h calculate to next address jmp y_add_1 ; if z = 00h increase y end_check: mov a, end_addr1 cmprs a, z ; check if z = low end address jmp aaa ; if not jump to checksum calculate mov a, end_addr2 cmprs a, y ; if yes, check if y = middle end address jmp aaa ; if not jump to checksum calculate jmp checksum_end ; if yes checksum calculated is done. y_add_1: incms y ; increase y nop jmp @b ; jump to checksum calculate checksum_end: ? ? end_user_code: ; label of program end
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 22 version 1.6 2.1.2 code option table code option content function description ihrc high speed internal 16mhz rc. xin/xout become to p2.0/p2.1 bi-direction i/o pins. high_clk 4m x?tal standard crystal /resonator (e.g. 4m) for external high clock oscillator. enable enable watchdog function watch_dog disable disable watchdog function enable enable rom code security function security disable disable rom code security function always_on force watch dog timer clock source come from int 16k rc. also int 16k rc never stop both in power down and green mode that means watch dog timer will always enable both in power down and green mode. int_16k_rc by_cpum enable or disable internal 16k (@ 3v) rc clock by cpum register enable enable low power function to save operating current low power disable disable low power function ? note: 1. in high noisy environment, set watch_dog as ?enable? and int_16k_rc as ?always_on? is strongly recommended. 2. fcpu code option is only available for high clock. fcpu of slow mode is flosc/4. 3. in high noisy environment, disable ?low power? is strongly recommended. 4. the side effect is to increase the lowest valid working voltage level if enable ?low power? code option. 5. enable ?low power? option will reduce operating current except in slow mode.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 23 version 1.6 2.1.3 data memory (ram) ) 128 x 8-bit ram ram location 000h general purpose area ; 000h~07fh of bank 0 = to store general . ; purpose data (128 bytes). 07fh . 080h system register ; 080h~0ffh of bank 0 = to store system . ; registers (128 bytes). bank 0 0ffh end of bank 0 area f00h lcd ram area ; bank 15 = to store lcd display data . ; (12 bytes). bank 15 f0bh end of lcd ram ;
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 24 version 1.6 2.1.4 system register 2.1.4.1 system register table 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 - - r z y - pflag rban k - lcdm1 - - - - - - 9 ampm ampch s ampck s adcm adck s cpm cpcks dfm adcdl adcdh lbtm - - - - - a - - - - - - - - - - - - - - - verfh b - - - - - - - - - - - - - - - pedge c - p1m p2m - - - - - intrq inten oscm - - - pcl pch d p0 p1 p2 - p4 p5 - - t0m t0c - - - - - stkp e - p1ur p2ur - - - - @yz - - - - - - - - f stk7l stk7h stk6l stk6h stk5l stk5h stk4l stk4h stk3l stk3h stk2l stk2h stk1l stk1h stk0l stk0h 2.1.4.2 system register description y, z = working, @yz and rom addressing register r = working register and rom look-up data buffer pflag = rom page and special flag regist er ampchs = pgia channel selection ampm = pgia mode register adcm = adc?s mode register ampcks = pgia clock selection cpm = charge pump mode adcks = adc clock selection dfm = decimation filter mode cpcks = charge pump clock selection adcdh = adc high-byte data buffer adcdl = adc low-byte data buffer p n ur = port n pull-up register p n m = port n input/output mode register intrq = interrupt request register p n = port n data buffer oscm = oscillator mode register inten = interrupt enable register pch, pcl = program counter lcdm1= lcd mode register stk0~stk7 = stack 0 ~ stack 7 buffer t0m = timer 0 mode register @yz = ram yz indirect addressing index pointer t0c = timer 0 counting register stkp = stack pointer buffer lbtm= low battery detect register
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 25 version 1.6 2.1.4.3 bit definition of system register address bit7 bit6 bit5 bit4 bi t3 bit2 bit1 bit0 r/w name 082h rbit7 rbit6 rbit5 rbit4 rb it3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 086h - - - - - c dc z r/w pflag 087h - - - - rbnks3 rbnks2 rbnks1 rbnks0 r/w rbank 089h - - lcdbnk - lcdenb lcdbia s lcdrate lcdclk r/w lcdm1 090h - bgrenb fds1 fds0 gs 2 gs1 gs0 ampenb r/w ampm 091h - - - - - chs2 chs1 chs0 r/w ampchs 092h - - - - - ampcks2 ampcks1 ampcks0 w ampcks 093h - - - - irvs rvs1 rvs0 adcenb r/w adcm 094h adcks7 adcks6 adcks5 adcks4 a dcks3 adcks2 adcks1 adcks0 w adcks 095h acmenb avddrenb avesel avenb cpst s cpauto cpon cprenb r/w cpm 096h - - - - cpcks3 cpcks2 cpcks1 cpcks0 w cpcks 097h - - - wrs0 drdy r/w dfm 098h adcb7 adcb6 adcb 5 adcb4 adcb3 adcb2 a dcb1 adcb0 r adcdl 099h adcb15 adcb14 a dcb13 adcb12 adcb11 adcb 10 adcb9 adcb8 r adcdh 09ah - - - - - lbto p 41io lbtenb r/w lbtm 0bfh pedgen - - p00g1 p00g0 - - - r/w pedge 0c1h - - - - p13m p12m p11m p10m r/w p1m 0c2h - - - - - - p21m p20m r/w p2m 0c8h - - - t0irq - - - p00irq r/w intrq 0c9h - - - t0ien - - - p00ien r/w inten 0cah wtcks wdrst wdarte - cpum0 clkmd stphx - r/w oscm 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh - - - - - pc10 pc9 pc8 r/w pch 0d0h - - - - - - - p00 r p0 0d1h - - - - p13 p12 p11 p10 r/w p1 0d2h - - - - - - p21 p20 r/w p2 0d4h - - - - - p42 p41 p40 r p4 0d5h - - - - - p52 p51 p50 r/w p5 0d8h t0enb t0rate2 t0rate1 t0rate0 - - - - r/w t0m 0d9h t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w t0c 0dfh gie - - - stkpb3 stkpb2 stkpb1 stkpb0 r/w stkp 0e1h - - - - p13r p12r p11r p10r w p1ur 0e2h - - - - - - p21r p20r w p2ur 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7p c3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h - - - s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6p c3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h - - - s6pc10 s6pc9 s6pc8 r/w stk6h 0f4h s5pc7 s5pc6 s5pc5 s5pc4 s5p c3 s5pc2 s5pc1 s5pc0 r/w stk5l 0f5h - - - s5pc10 s5pc9 s5pc8 r/w stk5h 0f6h s4pc7 s4pc6 s4pc5 s4pc4 s4p c3 s4pc2 s4pc1 s4pc0 r/w stk4l 0f7h - - - s4pc10 s4pc9 s4pc8 r/w stk4h 0f8h s3pc7 s3pc6 s3pc5 s3pc4 s3p c3 s3pc2 s3pc1 s3pc0 r/w stk3l 0f9h - - - s3pc10 s3pc9 s3pc8 r/w stk3h 0fah s2pc7 s2pc6 s2pc5 s2pc4 s2p c3 s2pc2 s2pc1 s2pc0 r/w stk2l 0fbh - - - s2pc10 s2pc9 s2pc8 r/w stk2h 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1p c3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh - - - s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0p c3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh - - - s0pc10 s0pc9 s0pc8 r/w stk0h
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 26 version 1.6 ? note: 1. to avoid system error, make sure to put all the ?0? and ?1? as it indicates in the above table . 2. all of register names had been declared in sn8asm assembler. 3. one-bit name had been declared in sn8asm assembler with ?f? prefix code. 4. ?b0bset?, ?b0bclr?, ?bset?, ?bclr? instruct ions are only available to the ?r/w? registers.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 27 version 1.6 2.1.4.4 accumulator the acc is an 8-bit data register responsible for trans ferring or manipulating data between alu and data memory. if the result of operating is zero (z) or there is carry (c or dc) occurrence, then these flags will be set to pflag register. acc is not in data memory (ram), so acc can?t be acce ss by ?b0mov? instruction dur ing the instant addressing mode. ? example: read and write acc value. ; read acc data and store in buf data memory mov buf, a ; write a immediate data into acc mov a, #0fh ; write acc data from buf data memory mov a, buf the system doesn?t store acc and pfla g value when interrupt executed. a cc and pflag data must be saved to other data memories by program. ? example: protect acc and working registers. .data accbuf ds 1 ; define accbuf for store acc data. pflagbuf ds 1 ; define pflagbuf for store pflag data. .code int_service: b0xch a, accbuf ; save acc in a buffer. b0mov a, pflag b0mov pflagbuf, a ; save pflag register in a buffer. ? ? b0mov a, pflagbuf b0mov pflag, a ; restore pflag register from buffer. b0xch a, accbuf ; restore acc from buffer. reti ; exit interrupt service vector ? note: to save and re-load acc data, users must use ?b0xch? instruction, or else the pflag re g iste r might be modified by acc operation.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 28 version 1.6 2.1.4.5 program flag the pflag register contains the arithmet ic status of alu operation, c, dc, z bits indicate the result status of alu operation. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag - - - - - c dc z read/write - - - - - r/w r/w r/w after reset - - - - - 0 0 0 bit 2 c: carry flag 1 = addition with carry, subtraction without borrowing, ro tation with shifting out logic ?1?, comparison result 0. 0 = addition without carry, s ubtraction with borrowing signal, rotation wi th shifting out logic ?0?, comparison result < 0. bit 1 dc: decimal carry flag 1 = addition with carry from low nibble, s ubtraction without borrow from high nibble. 0 = addition without carry from low nibble, subtraction with borrow from high nibble. bit 0 z: zero flag 1 = the result of an arithmetic/logic/branch operation is zero. 0 = the result of an arithmetic/logic/branch operation is not zero. ? note: refer to instruction set table for detailed information of c, dc and z flags.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 29 version 1.6 2.1.4.6 program counter the program counter (pc) is a 11-bit binary counter sepa rated into the high-byte 3 and the low-byte 8 bits. this counter is responsible for pointing a location in order to fe tch an instruction for kernel circuit. normally, the program counter is automatically incremented with eac h instruction during program execution. besides, it can be replaced with specific address by execut ing call or jmp instruction. when jmp or call instruction is executed, the desti nation address will be inserted to bit 0 ~ bit 10. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - - - - pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 after reset - - - - - 0 0 0 0 0 0 0 0 0 0 0 pch pcl ) one address skipping there are nine instructions (cmprs, incs, incms, de cs, decms, bts0, bts1, b0bts0, b0bts1) with one address skipping function. if the result of these instructions is true, the pc will add 2 steps to skip next instruction. if the condition of bit test instruction is true, the pc will add 2 steps to skip next instruction. b0bts1 fc ; to skip, if carry_flag = 1 jmp c0step ; else jump to c0step. ? ? c0step: nop b0mov a, buf0 ; move buf0 value to acc. b0bts0 fz ; to skip, if zero flag = 0. jmp c1step ; else jump to c1step. ? ? c1step: nop if the acc is equal to the immediat e data or memory, the pc will add 2 steps to skip next instruction. cmprs a, #12h ; to skip, if acc = 12h. jmp c0step ; else jump to c0step. ? ? c0step: nop
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 30 version 1.6 if the destination increased by 1, wh ich results overflow of 0xff to 0x00, the pc will add 2 steps to skip next instruction. incs instruction: incs buf0 jmp c0step ; jump to c0step if acc is not zero. ? ? c0step: nop incms instruction: incms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? ? c0step: nop if the destination decreased by 1, which results underflo w of 0x00 to 0xff, the pc will add 2 steps to skip next instruction. decs instruction: decs buf0 jmp c0step ; jump to c0step if acc is not zero. ? ? c0step: nop decms instruction: decms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? ? c0step: nop
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 31 version 1.6 ) multi-address jumping users can jump around the mult i-address by either jmp inst ruction or add m, a instruction (m = pcl) to activate multi-address jumping function. program counter can?t carr y to pch when pcl overflow automatically after executing addition instructions. users have to take care program coun ter result and adjust pch value by program. for jump table or others applications, users have to calculate pc value to avoid pcl overflow making pc error and program executing error. ? note: program counter can?t carry to pch when pcl overflow automaticall y after executin g addition instructions. users have to take care program counter result and adjust pch value by program. ? example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h mov a, #28h b0mov pcl, a ; jump to address 0328h ? ; pc = 0328h mov a, #00h b0mov pcl, a ; jump to address 0300h ? ? example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h b0add pcl, a ; pcl = pcl + ac c, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point ? ?
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 32 version 1.6 2.1.4.7 y, z registers the y and z registers are the 8-bit buffers. there ar e three major functions of these registers. z can be used as general working registers z can be used as ram data pointers with @yz register z can be used as rom data pointer with the movc instruction for look-up table 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset - - - - - - - - 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset - - - - - - - - example: uses y, z register as the data pointer to access data in the ram address 025h of bank0. b0mov y, #00h ; to set ram bank 0 for y register b0mov z, #25h ; to set location 25h for z register b0mov a, @yz ; to read a data into acc example: uses the y, z register as data pointer to clear the ram data. b0mov y, #0 ; y = 0, bank 0 b0mov z, #07fh ; z = 7fh, the last address of the data memory area clr_yz_buf: clr @yz ; clear @yz to be zero decms z ; z ? 1, if z= 0, finish the routine jmp clr_yz_buf ; not zero clr @yz end_clr: ; end of clear general purpose data memory area of bank 0 ?
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 33 version 1.6 2.1.4.8 r registers r register is an 8-bit buffer. there ar e two major functions of the register. z can be used as working register z for store high-byte data of look-up table (movc instruction executed, the high- byte data of specified rom address will be stored in r register and the low-byte data will be stored in acc). 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset - - - - - - - - ? note: please refer to the ?look-up table description? about r regi ster look-up table application.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 34 version 1.6 2.2 addressing mode 2.2.1 immediate addressing mode the immediate addressing mode uses an immediate data to set up the location in acc or specific ram. ? example: move the immediate data 12h to acc. mov a, #12h ; to set an immediate data 12h into acc. ? example: move the immediate data 12h to r register. b0mov r, #12h ; to set an immediate data 12h into r register. ? note: in immediate addressing mode application, th e specific ram must be 0x80~0x87 working register. 2.2.2 directly addressing mode the directly addressing mode moves the cont ent of ram location in or out of acc. ? example: move 0x12 ram location data into acc. b0mov a, 12h ; to get a content of ram location 0x12 of bank 0 and save in acc. ? example: move acc data into 0x12 ram location. b0mov 12h, a ; to get a content of acc and save in ram location 12h of bank 0. 2.2.3 indirectly addressing mode the indirectly addressing mode is to access the memory by the data pointer registers (y/z). ? example: indirectly addressing mode with @yz register. b0mov y, #0 ; to clear y register to access ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 35 version 1.6 2.3 stack operation 2.3.1 overview the stack buffer has 8-level. these buffers are designed to push and pop up program counter?s (pc) data when interrupt service routine and ?call? inst ruction are executed. the stkp register is a pointer designed to point active level in order to push or pop up data from stack buffer. the stknh and stknl are the stack buffers to store program counter (pc) data. ret / reti call / interrupt stkp = 7 stkp = 6 stkp = 5 stkp = 4 stack level stk7h stk6h stk5h stk4h stack buffer high byte pch stkp stk7l stk6l stk5l stk4l stack buffer low byte pcl stkp stkp - 1 stkp + 1 stkp = 3 stkp = 2 stkp = 1 stkp = 0 stk3l stk2l stk1l stk0l stk3h stk2h stk1h stk0h
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 36 version 1.6 2.3.2 stack registers the stack pointer (stkp) is a 3-bit register to store t he address used to access the st ack buffer, 11-bit data memory (stknh and stknl) set aside for temp orary storage of stack addresses. the two stack operations are writing to the top of the stac k (push) and reading from the top of stack (pop). push operation decrements the stkp and the pop operation increments each time. that makes the stkp always point to the top address of stack buffer and wr ite the last program counter val ue (pc) into the stack buffer. the program counter (pc) value is stored in the stack bu ffer before a call instruction ex ecuted or during interrupt service routine. stack operation is a lifo type (last in and first out). the stack pointer (stkp) and stack buffer (stknh and stknl) are located in t he system register area bank 0. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit[2:0] stkpbn: stack pointer (n = 0 ~ 2) bit 7 gie: global interrupt control bit. 0 = disable. 1 = enable. please refer to the interrupt chapter. ? example: stack pointer (stkp) r eset, we strongly recommended to clear the stack pointer in the beginning of the program. mov a, #00000111b b0mov stkp, a 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknh - - - - - snpc10 snpc9 snpc8 read/write - - - - - r/w r/w r/w after reset - - - - - 0 0 0 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknl snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 stkn = stknh , stknl (n = 7 ~ 0)
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 37 version 1.6 2.3.3 stack operation example the two kinds of stack-save operations re fer to the stack pointer (stkp) and writ e the content of program counter (pc) to the stack buffer are call instructi on and interrupt service. under each conditi on, the stkp decreases and points to the next available stack location. the stack buffer stor es the program counter about the op-code address. the stack-save operation is as the following table. stkp register stack buffer stack level stkpb2 stkpb1 stkpb0 high byte low byte description 0 1 1 1 free free - 1 1 1 0 stk0h stk0l - 2 1 0 1 stk1h stk1l - 3 1 0 0 stk2h stk2l - 4 0 1 1 stk3h stk3l - 5 0 1 0 stk4h stk4l - 6 0 0 1 stk5h stk5l - 7 0 0 0 stk6h stk6l - 8 1 1 1 stk7h stk7l - > 8 1 1 0 - - stack over, error there are stack-restore operations correspond to each push operation to restore the prog ram counter (pc). the reti instruction uses for interrupt service routine. the ret inst ruction is for call instruction. when a pop operation occurs, the stkp is incremented and points to the next free stack loca tion. the stack buffer restores the last program counter (pc) to the program counter registers. the stac k-restore operation is as the following table. stkp register stack buffer stack level stkpb2 stkpb1 stkpb0 high byte low byte description 8 1 1 1 stk7h stk7l - 7 0 0 0 stk6h stk6l - 6 0 0 1 stk5h stk5l - 5 0 1 0 stk4h stk4l - 4 0 1 1 stk3h stk3l - 3 1 0 0 stk2h stk2l - 2 1 0 1 stk1h stk1l - 1 1 1 0 stk0h stk0l - 0 1 1 1 free free -
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 38 version 1.6 3 3 3 reset 3.1 overview the system would be reset in three conditions as following. z power on reset z watchdog reset z brown out reset z external reset when any reset condition occurs, all syst em registers keep initial status, progra m stops and program counter is cleared. after reset status released, the system boots up and program starts to execute from org 0. finishing any reset sequence needs some time. the system provides complete procedures to make the power on reset successful. for different oscillat or types, the reset time is different. that causes the vdd rise rate and start-up time of different oscillator is not fixed. rc ty pe oscillator?s start-up time is very shor t, but the crystal type is longer. under clie nt terminal application, users have to take care the power on reset time for the master terminal requirement. the reset timing diagram is as following. vdd vss vdd vss watchdog normal run watchdog stop system normal run system stop lvd detect level external reset low detect external reset high detect watchdog overflow watchdog reset delay time external reset delay time power on delay time power external reset watchdog reset system status
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 39 version 1.6 3.2 power on reset the power on reset depend no lvd operation for most power- up situations. the power supplying to system is a rising curve and needs some time to achieve the normal voltage. power on reset sequence is as following. z power-up: system detects the power voltage up and waits for power stable. z external reset: system checks external reset pin status. if exter nal reset pin is not high level, the system keeps reset status and waits external reset pin released. z system initialization: all system registers is set as initia l conditions and system is ready. z oscillator warm up: oscillator operation is successfully and supply to system clock. z program executing: power on sequence is finished and program executes from org 0. 3.3 watchdog reset watchdog reset is a system protection. in normal condition, system works well and clears watchdog timer by program. under error condition, system is in unknown situation and watchdog can?t be clear by program before watchdog timer overflow. watchdog timer overflow occurs and the system is reset. after watchdog reset, the system restarts and returns normal mode. watchdog reset sequence is as following. z watchdog timer status: system checks watchdog timer overflow stat us. if watchdog timer ov erflow occurs, the system is reset. z system initialization: all system registers is set as initia l conditions and system is ready. z oscillator warm up: oscillator operation is successfully and supply to system clock. z program executing: power on sequence is finished and program executes from org 0. watchdog timer application note is as following. z before clearing watchdog timer, check i/o status and check ram contents c an improve system error. z don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. z clearing watchdog timer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? note: please refer to the ?watchdog timer? about watchdog timer detail information.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 40 version 1.6 3.4 brown out reset 3.4.1 brown out description the brown out reset is a power dropping condition. the powe r drops from normal voltage to low voltage by external factors (e.g. eft interference or extern al loading changed). the brown out reset would make the system not work well or executing program error. vdd vss v1 v2 v3 system work well area system work error area brown out reset diagram the power dropping might through the voltage range that ?s the system dead-band. the dead-band means the power range can?t offer the system minimum operation power re quirement. the above diagram is a typical brown out reset diagram. there is a serious noise under the vdd, and vdd voltage drops very deep. there is a dotted line to separate the system working area. the above area is the system work well area. the below area is the system work error area called dead-band. v1 doesn?t touch the below area and not effe ct the system operation. but the v2 and v3 is under the below area and may induce the system error occurrence. let system under dead-band includes some conditions. dc application: the power source of dc application is usually using battery . when low battery condition and mcu drive any loading, the power drops and keeps in dead-band. under the situat ion, the power won?t drop dee per and not touch the system reset voltage. that makes the system under dead-band. ac application: in ac power application, the dc power is regulated from ac power source. this kind of power usually couples with ac noise that makes the dc power dirty. or the external loading is very heavy, e. g. driving motor. the loading operating induces noise and overlaps with the dc power. vdd drop s by the noise, and the system works under unstable power situation. the power on duration and power down duration are longer in ac application. the system power on sequence protects the power on successful, but the power do wn situation is like dc low battery condition. when turn off the ac power, the vdd drops slowly and through the dead-band for a while.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 41 version 1.6 3.4.2 the system operating voltage decsription to improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level. differe nt system executing rates have differe nt system minimum operating voltage. the electrical characteristic section shows the system voltage to executing rate relationship. vdd (v) system rate (fcpu) system mini. operating voltage. system reset voltage. dead-band area normal operating area reset area normally the system operation voltage ar ea is higher than the system reset voltage to vdd, and the reset voltage is decided by lvd detect level. the system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage. the dead-band definition is the system minimum operat ing voltage above the system reset voltage. 3.4.3 brown out reset improvement how to improve the brown reset condition? there are some methods to improve brown out reset as following. z lvd reset z watchdog reset z reduce the system executing rate z external reset circuit. (zener diode reset circuit, voltage bias reset circuit, external reset ic) ? note: 1. the ? zener diode reset circuit?, ?volta g e bias reset circuit? and ?external reset ic? can completely improve the brown out reset, dc low battery and ac slow power down conditions. 2. for ac power application and enhance eft performance, the s y stem clock is 4mhz/4 ( 1 mips ) and use external reset ( ? zener diode reset circuit?, ?volta g e bias reset circuit?, ?external reset ic?). the structure can improve noise effective and get good eft characteristic.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 42 version 1.6 lvd reset: vdd vss system normal run system stop lvd detect voltage power on delay time power system status power is below lvd detect voltage and system reset. the lvd (low voltage detector) is built-in sonix 8-bit mcu to be brown out reset protection. when the vdd drops and is below lvd detect voltage, the lvd would be triggered, an d the system is reset. the lvd detect level is different by each mcu. the lvd voltage level is a point of volt age and not easy to cover all dead-band range. using lvd to improve brown out reset is depend on application requiremen t and environment. if the power variation is very deep, violent and trigger the lvd, the lvd ca n be the protection. if the power variation can touch the lvd detect level and make system work error, the lvd can? t be the protection and need to other reset methods. more detail lvd information is in the electrical characteristic section. watchdog reset: the watchdog timer is a protection to make sure the system executes well. normally the watchdog timer would be clear at one point of program. don?t clear the watchdog timer in several addresses. the system executes normally and the watchdog won?t reset system. when the system is under dea d-band and the execution error, the watchdog timer can?t be clear by program. the watchdog is continuously counti ng until overflow occurrence. the overflow signal of watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. this method also can improve brown out reset condition and make sure the system to return normal mode. if the system reset by watchdog and the power is still in dead-band, the system reset sequence won?t be successful and the system stays in reset status until the power return to normal range. reduce the system executing rate: if the system rate is fast and the dead-band exists, to redu ce the system executing rate can improve the dead-band. the lower system rate is with lower minimum operating voltage. select the power voltage that?s no dead-band issue and find out the mapping system rate. adjust the system ra te to the value and the syst em exits the dead-band issue. this way needs to modify whole program timing to fit the application requirement. external reset circuit: the external reset methods also can improve brown out rese t and is the complete solution. there are three external reset circuits to improve brown out reset including ?zener di ode reset circuit?, ?voltage bias reset circuit? and ?external reset ic?. these three reset structures use external rese t signal and control to make sure the mcu be reset under power dropping and under dead-band. the external rese t information is described in the next section.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 43 version 1.6 3.5 external reset external reset pin is schmitt trigger structure and low leve l active. the system is running when reset pin is high level voltage input. the reset pin receives the low voltage and the sy stem is reset. the external reset operation actives in power on and normal running mode. during system power-up, the ex ternal reset pin must be high level input, or the system keeps in reset status. exter nal reset sequence is as following. z external reset: system checks external reset pin status. if exter nal reset pin is not high level, the system keeps reset status and waits external reset pin released. z system initialization: all system registers is set as initia l conditions and system is ready. z oscillator warm up: oscillator operation is successfully and supply to system clock. z program executing: power on sequence is finished and program executes from org 0. the external reset can reset the system during power on duration, and good external reset circuit can protect the system to avoid working at unusual power condition, e.g. brown out reset in ac power application? 3.6 external reset circuit 3.6.1 simply rc reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf r2 100 ohm this is the basic reset circuit, and only includes r1 and c1. the rc circuit operation makes a slow rising signal into reset pin as power up. the reset signal is slower than vdd power up timing, and system occurs a power on signal from the timing difference. ? note: the reset circuit is no any protection against unusual power or brown out reset.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 44 version 1.6 3.6.2 diode & rc reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf diode r2 100 ohm this is the better reset circuit. the r1 and c1 circuit operation is like the simply reset circuit to make a power on signal. the reset circuit has a simply protection against unusual po wer. the diode offers a power positive path to conduct higher power to vdd. it is can make reset pin voltage le vel to synchronize with v dd voltage. the structure can improve slight brown out reset condition. ? note: the r2 100 ohm resistor of ?simpl y reset circuit? and ?diode & rc reset circuit? is necessar y to limit an y current flowin g into reset pin from external capacitor c in the event of reset pin breakdown due to electrostatic discharge (esd) or electrical over-stress (eos). 3.6.3 zener diode reset circuit mcu vdd vss vcc gnd r s t r1 33k ohm r3 40k ohm r2 10k ohm vz q1 e c b the zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely . use zener voltage to be the active level. when vdd vo ltage level is above ?vz + 0. 7v?, the c terminal of the pnp transistor outputs high voltage and mcu operates normal ly. when vdd is below ?vz + 0.7v?, the c terminal of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by zener specification. select the right zene r voltage to conform the application.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 45 version 1.6 3.6.4 voltage bias reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm r3 2k ohm r2 10k ohm q1 e c b the voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely . the operating voltage is not accurate as zener diode reset ci rcuit. use r1, r2 bias voltage to be the active level. when vdd voltage level is above or equal to ?0.7v x (r1 + r2) / r1?, the c terminal of the pnp transistor outputs high voltage and mcu operates normally. when vdd is below ?0.7v x (r 1 + r2) / r1?, the c terminal of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by r1, r2 resistances. select the right r1, r2 value to conform the application. in the circuit diagram condition, the mcu?s reset pin level varies with vdd voltage variation, and the differential voltage is 0.7v. if the vdd drops and the voltage lower than reset pin det ect level, the system would be reset. if want to make the reset active earlier, set the r2 > r1 and the cap between vd d and c terminal voltage is larger than 0.7v. the external reset circuit is with a stable current through r1 and r2 . for power consumption issue application, e.g. dc power system, the current must be considered to whole system power consumption. ? note: under unstable power condition as brown out re set, ?zener diode rest circuit? and ?volta g e bias reset circuit? can protects system no any error occurrence as power droppin g . when power drops below the reset detect volta g e, the s y stem reset would be tri gg ered, and then s y stem executes reset sequence. that makes sure the system work well under unstable power situation. 3.6.5 external reset ic mcu vdd vss vcc gnd r s t reset ic vdd vss rst bypass capacitor 0.1uf
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 46 version 1.6 4 4 4 system clock 4.1 overview the micro-controller is a dual clock sy stem. there are high-speed clock and low-speed clock. the high-speed clock is generated from the external oscillator circuit or on-chip 16mhz high-speed rc oscillator circuit (ihrc 16mhz). the low-speed clock is generated from on-chip low spee d rc oscillator circuit (i lrc 16khz@3v, 32khz@5v) both the high-speed clock and the low-sp eed clock can be system clock (fosc). the system clock in slow mode is divided by 4 to be the instruction cycle (fcpu). ) normal mode (high clock): fcpu = fhosc / 4 , (fhosc= 4m/8m crystal) fcpu = fhosc / 16 , (fhosc=ihrc) ) slow mode (low clock): fcpu = flosc/4. 4.2 clock block diagram z hosc: high_clk code option. z fhosc: external high-speed clock / internal high-speed rc clock. z flosc: internal low-speed rc clock .(about 16khz@3v, 32khz@5v) z fosc: system clock source. z fcpu: instruction cycle. fhosc. fcpu = fhosc/4 (fhosc=4m crystal) fcpu = fhosc/16 (fhosc=ihrc) flosc. fcpu = flosc/4 cpum[1:0] xin xout stphx hosc fosc fosc clkmd fcpu
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 47 version 1.6 4.3 oscm register the oscm register is an oscillator control regi ster. it controls oscillator status, system mode. 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm wtcks wdrst wdrate - cpum0 clkmd stphx 0 read/write r/w r/w r/w - r/w r/w r/w - after reset 0 0 0 - 0 0 0 - bit 1 stphx: external high-speed os cillator control bit. 0 = external high-speed oscillator free run. 1 = external high-speed oscillator free run stop. internal low-speed rc oscillator is still running. bit 2 clkmd: system high/low clock mode control bit. 0 = normal (dual) mode. syst em clock is high clock. 1 = slow mode. system clock is external low clock. bit[4:3] cpum0: cpu operating mode control bits. 0 = normal. 1 = sleep (power down) mode. bit5 wdrate: watchdog timer rate select bit. 0 = f cpu 2 14 1 = f cpu 2 8 bit6 wdrst: watchdog timer reset bit. 0 = no reset 1 = clear the watchdog timer?s counter. (the detail information is in watchdog timer chapter.) bit7 wtcks: watchdog clock source select bit. 0 = f cpu 1 = internal rc low clock. wtcks wtrate clkmd watchdog timer overflow time 0 0 0 1 / ( fcpu 2 14 16 ) = 293 ms, fosc=3.58mhz 0 1 0 1 / ( fcpu 2 8 16 ) = 500 ms, fosc=32768hz 0 0 1 1 / ( fcpu 2 14 16 ) = 65.5s, fosc=16khz@3v 0 1 1 1 / ( fcpu 2 8 16 ) = 1s, fosc=16khz@3v 1 - - 1 / ( 16k 512 16 ) ~ 0.5s @3v ? example: stop high-speed oscillator b0bset fstphx ; to stop exter nal high-speed oscillator only. ? example: when entering the power down mode (sl eep mode), both high-speed oscillator and internal low-speed oscillator will be stopped. b0bset fcpum0 ; to stop external high- speed oscillator and in ternal low-speed ; oscillator called powe r down mode (sleep mode).
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 48 version 1.6 4.4 system high clock the system high clock is from internal 16 mhz oscillator rc type or external oscilla tor. the high clock type is controlled by ?high_clk? code option. high_clk code option description ihrc the high clock is internal 16mhz oscillator rc type. xin and xout pins are general purpose i/o pins. 4m the high clock is external oscilla tor. the typical frequency is 4mhz. 4.4.1 internal high rc the chip is built-in rc type internal high clock (16mhz) controlled by ?ihrc_1 6m? code options. in ?ihrc_16m? mode, the system clock is from internal 16mhz rc type oscillator and xin / xout pins are general-purpose i/o pins. z ihrc: high clock is internal 16mhz oscillator rc ty pe. xin/xout pins are general purpose i/o pins. 4.4.2 external high clock external high clock includes three modules (crystal/ceramic , rc and external clock signal). the high clock oscillator module is controlled by high_clk code option. the start up ti me of crystal/ceramic and rc type oscillator is different. rc type oscillator?s start-up time is very short, but the crystal?s is longer. the osci llator start-up time decides reset time length. 4mhz ceramic 4mhz crystal
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 49 version 1.6 4.4.2.1 crystal/ceramic crystal/ceramic devices are driven by xin, xout pins . for high/normal/low frequency, the driving currents are different. high_clk code option supports different frequenci es. 4m option is for normal speed (ex. 4mhz). mcu vcc gnd c 20pf xin x o u t vdd vss c 20pf crystal ? note: connect the crystal/ceramic and c as near as po ssible to the xin/xout/vss pins of micro-controller. 4.4.2.2 external clock signal selecting external clock signal input to be system clock is by rc option of high_clk code opt ion. the external clock signal is input from xin pin. xout pin is general purpose i/o pin.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 50 version 1.6 4.5 system low clock the system low clock source is the internal low-speed oscill ator built in the micro-contro ller. the low-sp eed oscillator uses rc type oscillator circuit. the frequency is affect ed by the voltage and temperature of the system. in common condition, the frequency of the rc oscillator is about 16khz at 3v and 32khz at 5v. the relation between the rc frequency and voltage is as the following figure. internal low rc frequency 7.52 10.64 14.72 16.00 17.24 18.88 22.24 25.96 29.20 32.52 35.40 38.08 40.80 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 2.12.533.13.33.544.555.566.57 vdd (v) freq. (khz) ilrc the internal low rc supports watchdog clock source and system slow mode controlled by clkmd. ) flosc = internal low rc oscillator (about 16khz @3v, 32khz @5v). ) slow mode fcpu = flosc / 4 there are two conditions to stop internal low rc. one is power down mode, and the other is green mode of 32k mode and watchdog disable. if system is in 32k mode and watchdog disable, only 32k oscillator actives and system is under low power consumption. ? example: stop internal low-speed oscillator by power down mode. b0bset fcpum0 ; to stop external high- speed oscillator and in ternal low-speed ; oscillator called powe r down mode (sleep mode). ? note: the internal low-speed clock can?t be turned off individually. it is controlled by cpum0 bits of oscm register.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 51 version 1.6 4.5.1 system clock measurement under design period, the users can meas ure system clock speed by software instruction cycle (fcpu). this way is useful in low clock mode. ? example: fcpu instruction cycl e of external oscillator. b0bset p1m.0 ; set p1.0 to be output mode for outputting fcpu toggle signal. @@: b0bset p1.0 ; output fcpu toggle signal in low-sp eed clock mode. b0bclr p1.0 ; measure the fcpu frequency by oscilloscope. jmp @b
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 52 version 1.6 5 5 5 system operation mode 5.1 overview the chip is featured with low power consumption by switching around four different modes as following. z high-speed mode z low-speed mode z power-down mode (sleep mode) system mode switching diagram operating mode description mode normal slow power down (sleep) remark ehosc running by stphx stop ihrc running by stphx stop ilrc running running stop cpu instruction execut ing executing stop t0 timer *active *active inactive * active if t0enb=1 watchdog timer by watch_dog code option by watch_dog code option by watch_dog code option refer to code option description internal interrupt all active all active all inactive external interrupt all active all active all inactive wakeup source - - p0, p1, reset z ehosc: external high clock z ihrc: internal high clock (16m rc oscillator) z ilrc: internal low clock (16k rc oscillator at 3v, 32k at 5v) power down mode (sleep mode) slow mode normal mode clkmd = 1 clkmd = 0 p0, p1 wake-up function active. external reset circuit active. cpum0 = 1.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 53 version 1.6 5.2 system mode switching example ? example: switch normal/slow mode to power down (sleep) mode. b0bset fcpum0 ; set cpum0 = 1. ? note: during the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode. ? example: switch normal mode to slow mode. b0bset fclkmd ;to set clkmd = 1, change the system into slow mode b0bset fstphx ;to stop external high -speed oscillator for power saving. ? example: switch slow mode to normal mode ( the external high-speed oscillator is still running). b0bclr fclkmd ;to set clkmd = 0 ? example: switch slow mode to normal mode (the external high-speed oscillator stops). if external high clock stop and program want to switch back normal mode. it is necessary to delay at least 10ms for external clock stable. b0bclr fstphx ; turn on the external high-speed oscillator. mov a, #27 ; if vdd = 5v, internal rc=32khz (typical) will delay b0mov z, a @@: decms z ; 0.125ms x 81 = 10.125ms for external clock stable jmp @b ; b0bclr fclkmd ; change the system back to the normal mode -
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 54 version 1.6 5.3 wakeup 5.3.1 overview under power down mode (sleep mode) , program doesn?t ex ecute. the wakeup trigger can wake the system up to normal mode. the wakeup trigger sources are external trigger (p0, p1 level change) z power down mode is waked up to normal mode. the wakeup trigger is only external trigger (p0, p1 level change) 5.3.2 wakeup time when the system is in power down mo de (sleep mode), the high clock oscilla tor stops. when wake d up from power down mode, mcu waits for 2048 exte rnal high-speed oscillator clocks as the wake up time to stable the oscillator circuit. after the wakeup time, the system goes into the normal mode. the value of the wakeup time is as the following. the wakeup time = 1/fosc * 2048 (sec) + high clock start-up time ? note: the high clock start-up time is depended on the vdd and o scillator type of high clock. ? example: in power down mode (sleep mode), the sy stem is waked up. after the wakeup time, the system goes into normal mode. the wakeup time is as the following. the wakeup time = 1/fosc * 2048 = 0.512 ms (fosc = 4mhz) the total wakeup time = 0.512 ms + oscillator start-up time
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 55 version 1.6 6 6 6 interrupt 6.1 overview this mcu provides three interrupt sources, including one inte rnal interrupt (t0) and one external interrupt (int0). the external interrupt can wakeup the chip while the system is switched from power down mode to high-speed normal mode. once interrupt service is execut ed, the gie bit in stkp register will clear to ?0? for stopping other interrupt request. on the contrast, when in terrupt service exits, the gie bit will set to ?1? to accept the next interrupts? request. all of the interrupt request signals are stored in intrq register. ? note: the gie bit must enable during all interrupt operation. 6.2 inten interrupt enable register inten is the interrupt request control register including one internal interrupts, one exte rnal interrupts enable control bits. one of the register to be set ?1? is to enable the interrupt request function. once of the interrupt occur, the stack is incremented and program jump to org 8 to execute interrupt service routines. t he program exits the interrupt service routine when the returning interrupt service routine instruction (reti) is executed. 0c9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten - - - t0ien - - - p00ien read/write - - - r/w - - - r/w after reset - - - 0 - - - 0 bit 0 p00ien: external p0.0 interrupt (int0) control bit. 0 = disable int0 interrupt function. 1 = enable int0 interrupt function. bit 4 t0ien: t0 timer interrupt control bit. 0 = disable t0 interrupt function. 1 = enable t0 interrupt function. inten interrupt enable register interrupt enable gating intrq 2-bit latchs p00irq t0irq interrupt vector address (0008h) global interrupt request signal int0 trigger t0 time out
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 56 version 1.6 6.3 intrq interrupt request register intrq is the interrupt request flag register. the register incl udes all interrupt request indication flags. each one of the interrupt requests occurs, the bit of the intrq register would be set ?1?. the intrq value needs to be clear by programming after detecting the flag. in the interrupt vect or of program, users know the any interrupt requests occurring by the register and do the routi ne corresponding of the interrupt request. 0c8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq - - - t0irq - - - p00irq read/write - - - r/w - - - r/w after reset - - - 0 - - - 0 bit 0 p00irq: external p0.0 interrupt (int0) request flag. 0 = none int0 interrupt request. 1 = int0 interrupt request. bit 4 t0irq: t0 timer interrupt request flag. 0 = none t0 interrupt request. 1 = t0 interrupt request. 6.4 gie global interrupt operation gie is the global interrupt control bit. all interrupts start wo rk after the gie = 1 it is necessary for interrupt service request. one of the interrupt requests occurs, and the program co unter (pc) points to the interrupt vector (org 8) and the stack add 1 level. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit 7 gie: global interrupt control bit. 0 = disable global interrupt. 1 = enable global interrupt. ? example: set global interrupt control bit (gie). b0bset fgie ; enable gie ? note: the gie bit must enable during all interrupt operation.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 57 version 1.6 6.5 push, pop routine when any interrupt occurs, system will jump to org 8 and ex ecute interrupt service routine. it is necessary to save acc, pflag data. the chip doesn?t have any special inst ructions to process acc, pflag registers when into interrupt service routine. users have to save acc, pf lag by program, using ?b0xch? to save/load acc buffer, ?b0mov? to save/load pflag and avoid main routine er ror after interrupt service routine finishing. ? note: to save/load acc data, users must be ?b0xch? instruction, or else the pflag register might be modified by acc operation. ? example: store acc and paflg data by program when interrupt service routine executed. .data accbuf ds 1 ; accbuf is acc data buffer. pflagbuf ds 1 ; pflagbuf is pflag data buffer. .code org 0 jmp start org 8 jmp int_service org 10h start: ? int_service: b0xch a, accbuf ; save acc to accbuf buffer. b0mov a, pflag b0mov pflagbuf, a ; save pflag to pflagbuf buffer. ? ? b0mov a, pflagbuf b0mov pflag, a ; load pflag from pflagbuf buffer. b0xch a, accbuf ; load acc from accbuf buffer. reti ; exit interrupt service vector ? endp
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 58 version 1.6 6.6 int0 (p0.0) interrupt operation when the int0 trigger occurs, the p00irq will be set to ?1 ? no matter the p00ien is enable or disable. if the p00ien = 1 and the trigger event p00irq is also set to be ?1?. as t he result, the system will execute the interrupt vector (org 8). if the p00ien = 0 and the trigger event p00irq is still se t to be ?1?. moreover, the sy stem won?t execute interrupt vector even when the p00irq is set to be ?1?. users need to be cautious with the operation under multi-interrupt situation. ? note: the interrupt trigger direction of p0.0 is control by pedge register. 0bfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge pedgen - - p00g1 p00g0 - - - r/w - - r/w r/w - - - bit7 pedgen: interrupt and wakeup trigger edge control bit. 0 = disable edge trigger function. port 0: low-level wakeup trigger and falling edge interrupt trigger. port 1: low-level wakeup trigger. 1 = enable edge trigger function. p0.0: both wakeup and interrupt trigger are controlled by p00g1 and p00g0 bits. port 1: wakeup trigger is level change (falling or rising edge). bit[4:3] p00g[1:0]: port 0.0 edge select bits. 00 = reserved, 01 = falling edge 10 = rising edge, 11 = rising/falling bi-direction. ? example: setup int0 interrupt request and bi-direction edge trigger. mov a, #98h b0mov pedge, a ; set int0 interr upt trigger as bi-direction edge. b0bset fp00ien ; enable int0 interrupt service b0bclr fp00irq ; clear int0 interrupt request flag b0bset fgie ; enable gie ? example: int0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 fp00irq ; check p00irq jmp exit_int ; p00irq = 0, exit interrupt vector b0bclr fp00irq ; reset p00irq ? ; int0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 59 version 1.6 6.7 t0 interrupt operation when the t0c counter occurs overflow, the t0irq will be se t to ?1? however the t0ien is enable or disable. if the t0ien = 1, the trigger event will make the t0irq to be ?1? a nd the system enter interrupt ve ctor. if the t0ien = 0, the trigger event will make the t0irq to be ?1? but the system will not enter interr upt vector. users need to care for the operation under multi-interrupt situation. ? example: t0 interrupt request setup. b0bclr ft0ien ; disable t0 interrupt service b0bclr ft0enb ; disable t0 timer mov a, #20h ; b0mov t0m, a ; set t0 clock = fcpu / 64 mov a, #74h ; set t0c initial value = 74h b0mov t0c, a ; set t0 interval = 10 ms b0bset ft0ien ; enable t0 interrupt service b0bclr ft0irq ; clear t0 interrupt request flag b0bset ft0enb ; enable t0 timer b0bset fgie ; enable gie ? example: t0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 ft0irq ; check t0irq jmp exit_int ; t0irq = 0, exit interrupt vector b0bclr ft0irq ; reset t0irq mov a, #74h b0mov t0c, a ; reset t0c. ? ; t0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 60 version 1.6 6.8 multi-interrupt operation under certain condition, the software designer uses more than one interrupt requests. processing multi-interrupt request requires setting the priority of the interrupt requests. the irq flags of interrupts are controlled by the interrupt event. nevertheless, the irq flag ?1? doesn?t mean the syst em will execute the interrupt vector. in addition, which means the irq flags can be set ?1? by the events without enable the interrupt. once the event occurs, the irq will be logic ?1?. the irq and its trigger event relationship is as the below table. interrupt name trigger event description p00irq p0.0 trigger controlled by pedge t0irq t0c overflow for multi-interrupt conditions, two things need to be taking care of. one is to set the priority for these interrupt requests. two is using ien and irq flags to decide which interrupt to be executed. users have to check interrupt control bit and interrupt request flag in interrupt routine. ? example: check the interrupt request under multi-interrupt operation org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. intp00chk: ; check int0 interrupt request b0bts1 fp00ien ; check p00ien jmp intt0chk ; jump check to next interrupt b0bts0 fp00irq ; check p00irq jmp intp00 ; jump to int0 interrupt service routine intt0chk: ; check t0 interrupt request b0bts1 ft0ien ; check t0ien jmp int_exit ; jump to exit of irq b0bts0 ft0irq ; check t0irq jmp intt0 ; jump to t0 interrupt service routine int_exit: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 61 version 1.6 7 7 7 i/o port 7.1 i/o port mode the port direction is programmed by pnm register. a ll i/o ports can select input or output direction. 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1m - - - - p13m p12m p11m p10m read/write - - - - r/w r/w r/w r/w after reset - - - 0 0 0 0 0c2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2m - - - - - - p21m p20m read/write - - - - - - r/w r/w after reset - - - - - - 0 0 bit[7:0] pnm[7:0]: pn mode control bits. (n = 0~5). 0 = pn is input mode. 1 = pn is output mode. ? note: 1. users can program them by bit c ontrol instructions (b0bset, b0bclr). 2. port 4 is input only port. 3. port 5 is output only port. 4. port 2 is shared with xin and xout. ? example: i/o mode selecting clr p1m ; set all ports to be input mode. clr p2m mov a, #0ffh ; set all ports to be output mode. b0mov p1m,a b0mov p2m, a b0bclr p1m.0 ; set p1.0 to be input mode. b0bset p1m.0 ; set p1.0 to be output mode.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 62 version 1.6 7.2 i/o pull up register 0e1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1ur - - - - p13r p12r p11r p10r read/write - - - - w w w w after reset - - - - 0 0 0 0 0e2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2ur - - - - - - p21r p20r read/write - - - - - - w w after reset - - - - - - 0 0 ? note: pull up resistance of port 0 and port 4 is always existance. ? example: i/o pull up register mov a, #0ffh ; enable port1 pull-up register, b0mov p1ur,a
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 63 version 1.6 7.3 i/o port data register 0d0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 - - - - - - - p00 read/write - - - - - - - r/w after reset - - - - - - - 0 0d1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1 - - - - p13 p12 p11 p10 read/write - - - - r/w r/w r/w r/w after reset - - - - 0 0 0 0 0d2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2 - - - - - - p21 p20 read/write - - - - - - r/w r/w after reset - - - - - - 0 0 0d4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4 - - - - - p42 p41 p40 read/write - - - - - r r r after reset - - - - - 0 0 0 0d5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5 - - - - - p52 p51 p50 read/write - - - - - w w w after reset - - - - - 0 0 0 ? example: read data from input port. b0mov a, p0 ; read data from port 0 b0mov a, p1 ; read data from port 4 b0mov a, p4 ; read data from port 4 ? example: write data to output port. mov a, #0ffh ; write data ffh to all port. b0mov p1, a b0mov p5, a ? example: write one bit data to output port. b0bset p1.0 ; set p1.0 to be ?1?. b0bclr p1.0 ; set p1.0 to be ?0?.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 64 version 1.6 8 8 8 timers 8.1 watchdog timer (wdt) the watchdog timer (wdt) is a binary up counter designed for monitoring program execution. if the program goes into the unknown status by noise interferen ce, wdt overflow signal raises and resets mcu. the instruction that clears the watchdog timer (? b0bset fwdrst ?) s hould be executed within a certain per iod. if an instruction that clears the watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and system is restarted. 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm wtcks wdrst wdrate - cpum0 clkmd stphx 0 read/write r/w r/w r/w - r/w r/w r/w - after reset 0 0 0 - 0 0 0 - bit5 wdrate: watchdog timer rate select bit. 0 = f cpu 2 14 1 = f cpu 2 8 bit6 wdrst: watchdog timer reset bit. 0 = no reset 1 = clear the watchdog timer?s counter. (the detail information is in watchdog timer chapter.) bit7 wtcks: watchdog clock source select bit. 0 = f cpu 1 = internal rc low clock. watchdog timer overflow table. wtcks wtrate clkmd watchdog timer overflow time 0 0 0 1 / ( fcpu 2 14 16 ) = 293 ms, fosc=3.58mhz 0 1 0 1 / ( fcpu 2 8 16 ) = 500 ms, fosc=32768hz 0 0 1 1 / ( fcpu 2 14 16 ) = 65.5s, fosc=16khz@3v 0 1 1 1 / ( fcpu 2 8 16 ) = 1s, fosc=16khz@3v 1 - - 1 / ( 16k 512 16 ) ~ 0.5s @3v ? note: the watchdog timer can be enabled or disabled by the code option.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 65 version 1.6 watchdog timer application note is as following. z before clearing watchdog timer, check i/o status and check ram contents c an improve system error. z don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. z clearing watchdog timer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? example: an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: ? ; check i/o. ? ; check ram err: jmp $ ; i/o or ram error. program jump here and don?t ; clear watchdog. wait watchdog timer overflow to reset ic. correct: ; i/o and ram are correct. clear watchdog timer and ; execute program. b0bset fwdrst ; only one clearing watchdog timer of whole program. ? call sub1 call sub2 ? ? ? jmp main
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 66 version 1.6 8.2 timer 0 (t0) 8.2.1 overview the t0 is an 8-bit binary up timer and event counter. if t0 ti mer occurs an overflow (from ffh to 00h), it will continue counting and issue a time-out signal to trigger t0 interrupt to request interrupt service. the main purposes of the t0 timer is as following. ) 8-bit programmable up counting timer: generates interrupts at specific time intervals based on the selected clock frequency. ) green mode wakeup function: t0 can be green mode wake -up time as t0enb = 1. system will be wake-up by t0 time out. fcpu t0 rate (fcpu/2~fcpu/256) t0enb cpum0,1 t0c 8-bit binary up counting counter t0 time out load internal data bus 8.2.2 t0m mode register 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 - - - - read/write r/w r/w r/w r/w - - - - after reset 0 0 0 0 - - - - bit [6:4] t0rate[2:0]: t0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 t0enb: t0 counter control bit. 0 = disable t0 timer. 1 = enable t0 timer.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 67 version 1.6 8.2.3 t0c counting register t0c is an 8-bit counter register for t0 interval time control. 0d9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0c t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of t0c initial value is as following. t0c initial value = 256 - (t0 interrupt interval time * input clock) ? example: to set 10ms interval time for t0 interr upt. high clock is external 4mhz. fcpu=fosc/4. select t0rate=010 (fcpu/64). t0c initial value = 256 - (t0 interrupt interval time * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h the basic timer table interval time of t0. high speed mode (fcpu = 4mhz / 4) low speed mode (fcpu = 32768hz / 4) t0rate t0clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fcpu/256 65.536 ms 256 us 8000 ms 31250 us 001 fcpu/128 32.768 ms 128 us 4000 ms 15625 us 010 fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us 011 fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us 100 fcpu/16 4.096 ms 16 us 500 ms 1953.125 us 101 fcpu/8 2.048 ms 8 us 250 ms 976.563 us 110 fcpu/4 1.024 ms 4 us 125 ms 488.281 us 111 fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 68 version 1.6 8.2.4 t0 timer operation sequence t0 timer operation sequence of setup t0 timer is as following. ) stop t0 timer counting, disable t0 interrupt function and clear t0 interrupt request flag. b0bclr ft0enb ; t0 timer. b0bclr ft0ien ; t0 interrupt function is disabled. b0bclr ft0irq ; t0 interrupt request flag is cleared. ) set t0 timer rate. mov a, #0xxx0000b ;the t0 rate control bi ts exist in bit4~bit6 of t0m. the ; value is from x000xxxxb~x111xxxxb. b0mov t0m,a ; t0 timer is disabled. ) set t0 interrupt interval time. mov a,#7fh b0mov t0c,a ; set t0c value. ) set t0 timer function mode. b0bset ft0ien ; enable t0 interrupt function. ) enable t0 timer. b0bset ft0enb ; enable t0 timer.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 69 version 1.6 9 9 9 lcd driver there are 4 common pins and 12 segment pins in the sn8p 1917. the lcd scan timing is 1/4 duty and 1/2 bias or 1/3 bias structure to yield 48 dots lcd driver. 9.1 lcdm1 register lcdm1 register initial value = xx0x 0011 089h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcdm1 - - lcdbnk - lcdenb lc dbias lcdrate lcdclk r/w - - r/w - r/ w r/w r/w r/w after reset - - 0 - 0 0 1 1 bit5 lcdbnk: lcd blank control bit. 0 = normal display 1 = all of the lcd dots off. bit3 lcdenb: lcd driver enable control bit. 0 = disable 1 = enable. bit2 lcdbias: lcd bias selection bit 0 = lcd bias is 1/3 bias 1 = lcd bias is 1/2 bias bit1 lcdrate: lcd clock rate control when lcd clk=1. 0 = lcd clock= internal rc/ 64 1 = lcd clock= internal rc/ 32 bit1 lcdclk: lcd clock source slection control bit. 0 = lcd clock = external clock /2 ^14, frame rate = lcd clock / 4 ex. high clock = 4m, lcd clock = 244.14 hz , frame rate= 244.14/4=61.03 high clock = 3.58m, lcd clock = 218.51 hz , frame rate= 218.51/4=54.62 1 = lcd clock = internal rc /32(lcdrate= 1) or internal rc = 64 (lcdrate=0), frame rate = lcd clock/4 ? note 1: in dice form package of SN8P1917, two external pads of v1/v2 are available for fine tune the lcd bias voltage and current. ? note2: in 1/3 bias setting v1=1/3 vlcd, v2=2/3 vlcd. in 1/2 bias setting, please short v1 and v2, then v1=v2=1/2vlcd. ? note3: pads v1/v2 only available in dice form.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 70 version 1.6 9.2 lcd timing lcd timing table lcdclk lcd clock source lcdrate lcd clock frame=lcd clock/4 0 fhosc x 4m/2^14=244.14hz@4m 244.14/4=61.03hz 0 fhosc x 3.58m/2^14=218.51hz@3.58m 218.51/4=54.6hz 1 flosc 0 16k/64=250hz@3v 250/4=62.5hz 1 flosc 1 16k/32=500hz@3v 500/4=125hz 1 flosc 0 32k/64=500hz@5v 500/4=125hz 1 flosc 1 32k/32=1000hz@3v 1000/4=250hz lcd drive waveform, 1/4 duty, 1/2 bias com0 com1 com2 com3 seg0 (1010b) seg0 (0101b) 1 frame 1 frame lcd clock vlcd vss 1/2*vlcd vlcd vss 1/2*vlcd vlcd vss 1/2*vlcd vlcd vss 1/2*vlcd vlcd vss 1/2*vlcd on off on on on off off off vlcd vss 1/2*vlcd on on on on off off off off
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 71 version 1.6 lcd drive waveform, 1/4 duty, 1/3 bias vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd com0 com1 com2 com3 seg0 (1010b) seg0 (0101b) 1 frame 1 frame lcd clock on off on on on on on on on off off off off off off off
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 72 version 1.6 9.3 lcd ram location ram bank 15?s address vs. common/segment pin location bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 com0 com1 com2 com3 - - - - seg 0 00h.0 00h.1 00h.2 00h.3 - - - - seg 1 01h.0 01h.1 01h.2 01h.3 - - - - seg 2 02h.0 02h.1 02h.2 02h.3 - - - - seg 3 03h.0 03h.1 03h.2 03h.3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - seg 11 11h.0 11h.1 11h.2 11h.3 - - - - ? example: enable lcd function. set the lcd control bit (lcdenb) and program lcd ram to display lcd panel. b0bset flcdenb ; lcd driver.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 73 version 1.6 9.4 lcd circuit SN8P1917 in the lcd electric circuit, builds in 200k oh m voltage-division resistance. user can add resistance between vlcd / v2 / v1 / vss for more driving current. note: v1, v2 only available for dice form, not support package type. lcd circuit, 1/4 duty, 1/3 bias sn8p 1917 200k 200k 200k r r r 0.1u 0.1u vlcd v2 v1 vss 3 r 200k r 200k vlcd n consumptio current lcd ? ? ? ? ? ? + = note : if used external resister, the lcd current consumption from vlcd always existence, even under power down mode. note : v1=1/3*vlcd v2=2/3*vlcd
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 74 version 1.6 lcd circuit, 1/4 duty, 1/2 bias sn8p 1917 200k 200k r r 0.1u vlcd v2 v1 vss 2 r 200k r 200k vlcd n consumptio current lcd ? ? ? ? ? ? + = note : if used external resister, the lcd current consumption from vlcd always existence, even under power down mode. note : v1=v2=1/2*vlcd
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 75 version 1.6 1 1 1 0 0 0 charge-pump, pgia and adc 10.1 overview the SN8P1917 has a built-in voltage charge-pump/regulat or (cpr) to support a stable voltage 3.8v from pin avddr and 3.0v/1.5v from pin ave+ with maximum 10ma current driving capacity. this cpr provides stable voltage for internal circuits (pgia, adc) and external sensor (l oad cell or thermistor). the sn 8p1917 series also integrated analog-to-digital converters (adc) to achieve 16-bit performance and up to 62500-step resolution. the adc has 2 different input channel modes: (1) one fully differ ential inputs (2) two single-ended inputs. this adc is optimized for measuring low-level unipolar or bipolar signals in weight scale and medical applications. a very low noise chopper-stabilized programmable gain instrumentation amplif ier (pgia) with selectable gains of 1x, 12.5x, 50x, 100x, and 200x in the adc to accommodate these applications. 10.2 analog input following diagram illustrates a block diagram of the pgia and adc module. the front end consists of a multiplexer for input channel selection, a pgia (programm able gain instrumentation amplifier), and the ? adc modulator. to obtain maximum range of adc output, the adc maximum input signal voltage v (x+, x-) should be close to but can?t over the reference voltage v(r+, r-), choosing a suitable reference voltage and a suitable gain of pgia can reach this purpose. the relative control bits are rvs [1:0 ] bits (reference voltage selection) in adcm register and gs[2:0] bits (gain selection) in ampm register. block diagram of adc module ? note 1: the low pass filter (r, r and c) will filter out chopper frequency of pgia. ? note 2: the recommend value of c is 0.01 f. this capacitor needs to place as close chip as possible. pgia pgia ? adc module x- x+ adcdb ampcks ampm ai2+ ai2- ai2+ ai+ ai2- ai- r- r+ adcks adm c
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 76 version 1.6 10.3 voltage charge pump / regulator (cpr) SN8P1917 is built in a cpr, which can provide a stable 3.8v (pin avddr) and 3.0v/1.5v (pin ave+) with maximum 10ma current driving capacity. regist er cpm can enable or disable cpr and controls cpr working mode, another register cpcks sets cpr working clock to 4khz. because the power of pgia and adc is come from avddr, turn on avddr (avddrenb = 1) first before enabling pgia and ad c. the avddr voltage was regulated from avddcp. in addition, the cp will need at least 10ms for output voltage stabilization after set cprenb to high. 10.3.1 cpm-charge pump mode register 095h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cpm acmenb avddrenb avesel avenb c psts cpauto cpon cprenb r/w r/w r/w r/w r/w r r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit0: cprenb: charge pump / regulator function enable control bit. 0 = disable charge pump and regulator, 1 = enable charge pump and regular. bit1: cpon: change pump always on function control bit (cprenb must = ?1?) 0 = charge pump on / off controlled by bit cpauto. 1 = always turn on the charge pump regulator. bit2: cpauto: charge pump auto mode function control bit 0 = disable charge pump auto mode. 1 = enable charge pump auto mode. bit3: cpsts: charge-pump status bit in auto mode (only available when cpauto = ?1?) 0 = charge-pump is off in auto mode. 1 = charge-pump is on in auto mode. bit4: avenb: ave+ voltage output control bit. 0 = disable ave+ output voltage 1 = enable ave+ output voltage bit5: avesel : ave+ voltage selection control bit. 0 = ave+ output 1.5v 1 = ave+ output 3.0v bit6: avddrenb: regulator (avddr) voltage enable control bit. 0 = disable regulator and avddr output voltage 3.8v 1 = enable regulator and avddr output voltage 3.8v bit7: acmenb: analog common mode (acm) voltage enable control bit. 0 = disable analog common mode and acm output voltage 1.2v 1 = enable analog common mode and acm output voltage 1.2v ? note1: 30ms delay is necessary for output vo ltage stabilization after set cprenb = ?1?. ? note2: all current consumptions from avddr and ave+ (including pgia and adc) will time 2, when charge pump was enabled. ? note3: before enable charge pump/regulator , mu st enable band gap reference (bgrenb=1) first. ? note4: before enable pgia and adc , must enable band gap refere nce (bgrenb=1), acm (acmenb=1) and avddr(avddrenb). ? note5: cpr, pgia and adc can work in slow m ode, but cpcks, ampcks register value must be reassigned .
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 77 version 1.6 bit cprenb, cpon, and cpauto are charge-pump working mo de control bit. by these three bits, charge-pump can be set as off, always on, or auto mode. cprenb cpon cpauto avddrenb charge-pump status regulator status cpsts avddr pgia, adc function 0 x x 0 off off n/a 0v not available 1 0 0 1 off on n/a see note1 see note1 1 0 1 1 auto mode on 0/1 3.8v available 1 1 0 1 on on n/a 3.8v available in auto mode, charge-pump on/off depended on vdd voltage. auto-mode description: cprenb cpon cpauto avddrenb vdd charge-pump status cpsts regulator status avddr output pgia, adc function >4.1v off 0 on 3.8v available 1 0 1 1 Q 4.1v on 1 on 3.8v available ? note 1: when charge-pump is off and regulator is on, vdd voltage must be higher than 4.1v to make sure avddr output voltage for pgia, and adc functions are working well. cprenb cpon cpauto avddrenb vdd charge-pump status regulator status avddr output pgia, adc function >4.1v off on 3.8v available 1 0 0 1 Q 4.1v off on vdd not available ? note 1: for normally application, set cp as auto mode (cpauto = 1) is strongly recommended. ? note 2: if vdd is higher than 5.0v, don?t set charge-pump as always on mode. ? note 3: band gap reference voltage must be enable (fbrgenb), before following function accessing: (reference ampm register for detail information) (1) charge pump /regulator. (2) pgia function. (3) 16- bit adc function. (4) low battery detect function
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 78 version 1.6 10.3.2 cpcks-charge pump clock register 096h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cpcks cpcks3 cpcks2 cpcks1 cpcks0 r/w w w w w after reset 0 0 0 0 cpcks [4:0] register sets the charge-pump working clock; t he suggestion charge-pump clock is 13k~15.6 hz.@ normal mode, 2k@slow mode charge-pump clock= fcpu / 4 / (2^cpcks[3:0]) refer to the following table for cpcks [3:0] register value setting in different fosc frequency. high clock cpcks3 cpcks2 cpcks1 cpcks0 2m 3.58m 4m/ihrc 8m 0 0 0 0 125k 223.75k 250k 500k 0 0 0 1 62.5k 111.88k 125k 250k 0 0 1 0 31.25k 55.94k 62.5k 125k 0 0 1 1 15.625k 27.97k 31.25k 62.5k 0 1 0 0 7.8125k 13.985k 15.625k 31.25k 0 1 0 1 3.90625k 6.99k 7.8125k 15.625k 0 1 1 0 1.953215k 3.495k 3.90625k 7.8125k 0 1 1 1 0.976k 1.75k 1.953215k 3.90625k 1 0 0 0 0.488k 0.875k 0.976k 1.953215k 1 0 0 1 0.244k 0.438k 0.488k 0.976k 1 0 1 0 0.122k 0.219k 0.244k 0.488k 1 0 1 1 0.61k 0.11k 0.122k 0.244k 1 1 0 0 0.3k 0.055k 0.061k 0.122k 1 1 0 1 0.15k 0.028k 0.03k 0.61k 1 1 1 0 0.075k 0.014k 0.015k 0.3k 1 1 1 1 0.037k 0.007k 0.008k 0.15k ? note1: when enable charge pump, set charge pump clock as ?1011? to avoid vdd dropped. ? note2: in general application, cp working clock is about 13k~15k hz in normal mode, 2k hz in slow mode (internal low clock mode). ? note3: the faster of charge pump clock, ave+ can load more current.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 79 version 1.6 example: charge-pump setting (fosc = 4m x?tal) @cpreg_init: xb0bset fbgrenb ;enable band gap reference voltage. mov a, #00001011b xb0mov cpcks, a ; set cpcks as sl owest clock to void vdd dropping. mov a, #00100100b ; xb0mov cpm, a ; set ave+=3.0v ,cp as auto mode and disable avddr, ave+, acm voltage and befo re enable charge pump @cp_enable: xb0bset fcprenb ; enable charge-pump call @wait_200ms ; delay 200ms for charge-pump stabilize mov a, #0000100b xb0mov cpcks, a ; set cpcks as 15.6k for 10ma current loading. call @wait_100ms ; delay 5m s for acm voltage stabilize @acm_enable: xb0bset facmenb ; enable acm voltage=1.2v call @wait_5ms ; delay 5ms for acm voltage stabilize @avddr_enable: xb0bset favddrenb ; enable avddr voltage=3.8v call @wait_50ms ; delay 50ms for avddr voltage stabilize @ave_enable: xb0bset favenb ; enable ave+ voltage=3.0v/1.5v call @wait_50ms ; delay 50ms for ave+ voltage stabilize ? ? ? note1: the charge pump delay (200ms and 100ms) can avoid vdd drop when cr2032 batter y application. if vdd source came from aa or aaa dry battery, the delay time can be shorten to 50ms.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 80 version 1.6 10.4 pgia -programmable gain instrumentation amplifier SN8P1917 includes a low noise chopper-stabilized programmabl e gain instrumentation amplifier (pgia) with selection gains of 1x, 12.5x, 50x, 100x, and 200x by register ampm. t he pgia also provides two types channel selection mode: (1) one fully differential input (2) two single-en ded inputs, it was defined by register ampchs. 10.4.1 ampm- amplifier mode register 090h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ampm - bgrenb fds1 fds0 gs2 gs1 gs0 ampenb r/w - r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 1 1 1 0 bit0: ampenb: pgia function enable control bit. 0 = disable pgia function 1 = enable pgia function bit[3:1]: gs [2:0]: pgia gain selection control bit gs [2:0] pgia gain 000 12.5 001 50 010 100 011 200 100,101,110 reserved 111 1 ? note: when selected gain is 1x, pgia can be disabled (ampenb=0) for power saving. bit[5:4] fds [1:0]: chopper low frequency setting note:set fds[1:0] = ?11? for all applications. bit6: bgrenb: band gap reference voltage enable control bit. 0 = disable band gap reference voltage 1 = enable band gap reference voltage ? note1: band gap reference voltage must be enable (fbrgenb), before following function accessing 1. charge pump /regulator. 2. pgia function. 3. 16- bit adc function. 4. low battery detect function ? note2: pgia can?t work in slow mode, unless gain selection is 1x.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 81 version 1.6 10.4.2 ampcks- pgia clock selection 092h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ampcks - - - - - ampcks1 ampcks1 ampcks0 r/w - - - - - w w w after reset - - - - - 0 0 0 bit[2:0] ampcks [2:0] register sets the pgia chopper working clock. the suggestion chopper clock is 1.95k hz.@ 4mhz, 1.74k @ 3.58mhz. pgia clock= fcpu / 32 / (2^ampcks) refer to the following table for ampcks [2:0] register value setting in different fosc frequency. high clock ampcks2 amcks1 ampcks0 2m 3.58m 4m/ihrc 8m 0 0 0 15.625k 27.968k 31.25k 62.5k 0 0 1 7.8125k 13.98k 15.625k 31.25k 0 1 0 3.90625k 6.99k 7.8125k 15.625k 0 1 1 1.953125k 3.49k 3.90625k 7.8125k 1 0 0 976hz 1.748k 1.953125k 3.90625k 1 0 1 488hz 874hz 976hz 1.953125k 1 1 0 244hz 437hz 488hz 976hz 1 1 1 122hz 218hz 244hz 488hz ? note: in general application, set pgia chopper work ing clock is ~2k hz, but set clock to 250hz when hi g h clock is 32768 crystal or in internal low clock mode.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 82 version 1.6 10.4.3 ampchs-pgia channel selection 091h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ampchs - - - - - chs2 chs1 chs0 - - - - - r/w r/w r/w chs [2:0]: pgia channel selection chs [2:0] selected channel v (x+, x-) output input-signal type 000 ai+, ai- v (ai+, ai-) pgia gain differential 001 ai+, acm v (ai+, acm) pgia gain single-ended 010 ai-, acm v (ai-, acm) pgia gain single-ended 011 acm, acm v (acm, acm) pgia gain input-short 100 reserved - - 101 temperature sensor v (v ts , 0.8v) 1 n/a 110,111 ? note 1: v (ai+, ai-) = (ai+ voltage - ai- voltage) ? note 2: v (ai-, acm) = (ai- voltage - acm voltage) ? note 3: the purpose of input-short mode is only for pgia offset testing. ? note 4: when cpr is disable or s y stem in stop mode, si g nal on analo g input pins must be zero ( ?0?v, including ai+, ai-, x+, x-, r+ and r-) or it w ill cause the current consum ption from these pins. ampchs[2:0]=?000? ampchs[2:0]=?001? ampchs[2:0]=?010? ampchs[2:0]=?011? pgia ai+ ai- adc x+ x- ref+ ref- pgia ai+ adc x+ x- ref+ ref- acm pgia ai- adc x+ x- ref+ ref- acm pgia adc x+ x- ref+ ref- acm
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 83 version 1.6 10.4.4 temperature sensor (ts) in applications, sensor characteristic might change in differ ent temperature also. to get the temperature information, SN8P1917 build in a temperature senor (ts) for temperatur e measurement. select the respective pgia channel to access the temperature sensor adc output. ampchs[2:0]=?101? ? note1: when selected temperature sensor, pgia gain must set to 1x, or the result will be incorrect. ? note2: under this setting, x+ will be th e v(ts) voltage, and x- will be 0.4v. ? note3: the temperature sensor was j ust a reference data not real air temperature. for precision application, please use external thermister sensor. in 25c, v(ts) will be about 0.8v, and if temperature rise 10 c, v(ts) will decrease about 15mv, if if temperature drop 10c, v(ts) will increase about 15mv, example: temperature v(ts) v(ref+,ref-) adc output 15 0.815v 0.8v 16211 25 0.800v 0.8v 15625 35 0.785v 0.8v 15039 by adc output of v(ts), can get temperatur e information and compensation the system. ? note1: the v ( ts ) volta g e and temperature curve of each chip mi g ht different. calibration in room temperature is necessary when application temperature sensor. ? note2: 1.5mv/c was t y pical temperature parameter onl y of temperature sensor, ever y sin g le chip was different to each other. 1x adc x+ x- ref+ ref- avddr avss 0.4v ts
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 84 version 1.6 example: pgia setting (fosc = 4m x?tal) @cpreg_init: xb0bset fbgrenb ;enable band gap reference voltage. mov a, #00001011b xb0mov cpcks, a ; set cpcks as sl owest clock to void vdd dropping. mov a, #00100100b ; xb0mov cpm, a ; set ave+=3.0v ,cp as auto mode and disable avddr, ave+, acm voltage and befo re enable charge pump @cp_enable: xb0bset fcprenb ; enable charge-pump call @wait_200ms ; delay 200ms for charge-pump stabilize mov a, #0000100b xb0mov cpcks, a ; set cpcks as 15.6k for 10ma current loading. call @wait_100ms ; delay 5m s for acm voltage stabilize @acm_enable: xb0bset facmenb ; enable acm voltage=1.2v call @wait_5ms ; delay 5ms for acm voltage stabilize @avddr_enable: xb0bset favddrenb ; enable avddr voltage=3.8v call @wait_50ms ; delay 50ms for avddr voltage stabilize @ave_enable: xb0bset favenb ; enable ave+ voltage=3.0v/1.5v call @wait_50ms ; delay 50ms for ave+ voltage stabilize @pgia_init: mov a, #01110110b xb0mov ampm, a ; enable band gap, set :fds=?11? and pgia gain=200 mov a, #00000100b xb0mov ampcks, a ; set ampcks = ?100? fo r pgia working clock = 1.9k @ 4m x?tal mov a, #00h xb0mov ampchs, a ; selected pgia differential input channel= ai+, ai- @pgia_enable: xb0bset fampenb ; enable pgia function ? ; v (x+, x-) output = v (ai+, ai-) x 200 ? note 1: enable charge-pump/regulator before pgia working ? note 2: please set pgia relative registers first, then enable pgia function bit.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 85 version 1.6 example: pgia channel change: @pgia_init: mov a, #01110110b xb0mov ampm, a ; enable band gap, set :fds=?11? and pgia gain=200 mov a, #00000100b xb0mov ampcks, a ; set ampcks = ?100? fo r pgia working clock = 1.9k @ 4m x?tal mov a, #00000000b xb0mov ampchs, a ; selected pgia differential input channel= ai+, ai- @pgia_enable: xb0bset fampenb ; enable pgia function ? ; v (x+, x-) output = v (ai+, ai-) x 200 @pgia_sensor: mov a, #01110111b ;don?t disable pgia when change pgia ch. xb0mov ampm, a ; enable band gap, set :fds=?11? and pgia gain=200 mov a, #00000000b xb0mov ampchs, a ; selected pgia as differential channel. ? ; v (x+, x-) output = v(ai+,ai-) x 200 @pgia_ts: mov a, #01110001b ;don?t disable pgia when change pgia ch. xb0mov ampm, a ; enable band gap, set :fds=?11? and pgia gain=1x mov a, #00000101b xb0mov ampchs, a ; selected pgia as temperature sensor ch. ? ; v (x+, x-) output = v (ts, 0.4) x 1.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 86 version 1.6 10.5 16-bit adc 10.5.1 adcm- adc mode register 093h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcm - - - - irvs rvs1 rvs0 adcenb r/w - - - - r/w r/w r/w r/w - - - - 0 0 0 0 bit0: adcenb: adc function control bit: 0 = disable 16-bit adc, 1 = enable 16-bit adc bit1: rvs 0 : adc reference voltage selection bit 0 = selection adc as normal operation from x+,x-. 1 = selection adc as vdd voltage detect bit2: rvs 1 : adc reference voltage selection bit 1 0 = selection adc reference voltage from external reference r+,r-. 1 = selection adc reference voltage from internal reference bit3: irvs: internal reference voltage selection. 0 = internal reference voltage v(ref+,ref-) is ave+/1.33 (when ave+=3.0v, v(ref+,ref-)=0.4v) 1 = internal reference voltage v(ref+,ref-) is ave+/2.660. (when ave+=3.0v, v(ref+,ref-)=0.8v) ad reference voltage ad channel input irvs rvs1 rvs0 ref+ ref- adcin+ adcin- note x 0 0 r+ r- v (x+, x-) < v (r+, r-) 0 1 0 0.8v 0.4v v (x+, x-) < 0.4v (ave+=3.0v) 1 1 0 1.2v 0.4v v (x+, x-) < 0.8v (ave+=3.0v) 1 1 0 0.6v 0.2v x+ x- v (x+, x-) < 0.4v (ave+=1.5v) x 0 1 r+ r- 0 1 1 0.8v 0.4v 1 1 1 1.2v 0.4v vdd *3/16 vdd* 2/16 adc input = 1/16 vdd for battery monitor (ave+=3.0v) ? note1: the adc conversion data is combined with adcdh and adcdl register in 2?s compliment with sign bit numerical format, and bit adcb15 is the sign bit of adc data. refer to followin g formula to calculate adc conversion data value. ? note2: the internal reference volta g e is divided from ave+, so the volta g e will follow the chan g in g with ave+(3.0v/1.5v). 31250 ) ( ) ( ) ( ) ( ) ( ) ( 31250 ) ( ) ( ) ( ) ( ) ( ) ( x ref ref adcin adcin iondata adcconvers adcin adcin x ref ref adcin adcin iondata adcconvers adcin adcin ? ? + ? ? + ? = ? ? < + ? ? + ? ? + + = ? ? > + ? note2: the internal 1.2v, 0.8v and 0.4v reference voltage are generated from band gap reference voltage.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 87 version 1.6 external and internal reference circuit table: external reference circuit internal reference circuit rvs1=0 rvs1=1, irvs=1, ave+=3.0v irvs=1, ave+=1.5v irvs=0,ave+=3.0v adcm=#xxxxx00xb, v(ref+, ref-) = v(r+, r-), a dc reference voltage from external r+,r-. adcm=#xxxx110xb, v(ref+, ref-) = v(1. 2v, 0.4v)=0.8v (ave+=3.0v) adc re ference voltage from internal 1.2v and 0.4v. pgia pgia adc x+ x- ref+ ref- r- r+ avss ave+ r+ r- pgia pgia adc x+ x- ref+ ref- 0.4v 1.2v avss ave+=3.0v 1.2v 0.4v ref- ref+ avss 0.6v 0.2v ref- ref+ ave+=1.5v avss 0.4v 0.8v ave+=3.0v ref+ ref-
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 88 version 1.6 adcm=#xxxx010xb, v(ref+, ref-) = v(0. 8v, 0.4v)=0.4v (ave+=3 .0v), adc reference voltage from internal 0.8v and 0.4v. adcm=#xxxx111xb, v(ref+, ref-) = v(1. 2v, 0.4v)=0.8v (ave+=3 .0v), adc reference voltage from internal 1.2v and 0.4v, and adc output is voltage measurement result. pgia pgia adc x+ x- ref+ ref- 0.4v 1.2v avss vdd 3/16vdd 2/16vdd pgia pgia adc x+ x- ref+ ref- 0.4v 0.8v
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 89 version 1.6 10.5.2 adcks- adc clock register 094h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcks adcks7 adcks6 adcks5 adcks4 adcks3 adcks2 adcks1 adcks0 w w w w w w w w after reset 0 0 0 0 0 0 0 0 adcks [7:0] register sets the adc working clock, the suggestion adc clock is 100k hz. refer the following table for adcks [7:0] regist er value setting in different fosc frequency. adc clock= (fosc / (256-adcks [7:0]))/2 adcks [7:0] f osc adc working clock 246 4m (4m / 10)/2 = 200k 236 4m (4m / 20)/2 = 100k 243 4m (4m / 13)/2 = 154k 231 4m (4m / 25)/2 = 80k adcks [7:0] f osc adc working clock 236 8m (8m / 20)/2 = 200k 216 8m (8m / 40)/2 = 100k 231 8m (8m / 25)/2 = 160k 206 8m (8m / 50)/2 = 80k ? note: in general application, adc working clock is 100k hz.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 90 version 1.6 10.5.3 adcdl- adc low-byte data register 098h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcdl adcb7 adcb6 adcb 5 adcb4 adcb3 a dcb2 adcb1 adcb0 r r r r r r r r after reset 0 0 0 0 0 0 0 0 10.5.4 adcdh- adc high-byte data register 099h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcdh adcb15 adcb14 adcb13 adcb12 adcb11 adcb10 adcb8 adcb9 r r r r r r r r after reset 0 0 0 0 0 0 0 0 adcdl [7:0]: output low byte data of adc conversion word. adcdh [7:0]: output high byte data of adc conversion word. . ? note1: adcdl [7:0] and adcdh [7:0] are both read only registers. ? note2: the adc conversion data is combined wi th adcdh, adcdl in 2?s compliment with sign bit numerical format, and bit adcb15 is the sign bit of adc data. adcb15=0 means data is positive value, adcb15=1 means data is negative value. ? note3: the positive full-scale-output val ue of adc conversion is 0x7a12. ? note4: the negative full-scale-output value of adc conversion is 0x85ee. ? note5: because of the adc design limitation, the ad c linear range is +28125~-28125 (decimal). the max adc output must keep inside this range. adc conversion data (2?s compliment, hexadecimal) decimal value 0x7a12 31250 ? ? 0x4000 16384 ? ? 0x1000 4096 ? ? 0x0002 2 0x0001 1 0x0000 0 0xffff -1 0xfffe -2 ? ? 0xf000 -4096 ? ? 0xc000 -16384 ? ? 0x85ee -31250
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 91 version 1.6 10.5.5 dfm-adc digital filter mode register 097h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dfm - - - - - wrs0 - drdy - - - - - r/w - r/w bit0: drdy: adc data ready bit. 1 = adc output (update) new conv ersion data to adcdh, adcdl. 0 = adcdh, adcdl conversi on data are not ready. bit2: wrs [1:0]: adc output word rate selection: output word rate wrs0 adc clock = 200k adc clock = 100k adc clock = 80k 0 50hz 25 hz 20 hz 1 25hz 12.5 hz 10 hz ? note 1: when stod=0, the adc is designed for continuous mode, so it needn?t read each conversion data every time. user only needs to read the data when conversion result is required. note that if the conversion data is not read immediately, it could be lost and be replaced b y the next new conversion data. ? note2: when stod = 1, althou g h no more conversion word will update to adc output buf fer, but adc is still working and will output conv ersion word when stod= 0. ? note 3: ac power 50 hz noise will be filt er out when output word rate = 25hz ? note 4: ac power 60 hz noise will be filt er out when output word rate = 20hz ? note 5: both ac power 50 hz and 60 hz noise w ill be filter out when output word rate = 10hz ? note 6: clear bit drdy a fter got adc data or this bit will keep high all the time. ? note 7: adjust adc clock (adcks) and bit wrs0 can get suitable adc output word rate.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 92 version 1.6 example: charge-pump, pgia and adc setting (fosc = 4m x?tal) @cpreg_init: xb0bset fbgrenb ;enable band gap reference voltage. mov a, #00001011b xb0mov cpcks, a ; set cpcks as sl owest clock to void vdd dropping. mov a, #00100100b ; xb0mov cpm, a ; set ave+=3.0v ,cp as auto mode and disable avddr, ave+, acm voltage and befo re enable charge pump @cp_enable: xb0bset fcprenb ; enable charge-pump call @wait_200ms ; delay 200ms for charge-pump stabilize mov a, #0000100b xb0mov cpcks, a ; set cpcks as 15.6k for 10ma current loading. call @wait_100ms ; delay 5m s for acm voltage stabilize @acm_enable: xb0bset facmenb ; enable acm voltage=1.2v call @wait_5ms ; delay 5ms for acm voltage stabilize @avddr_enable: xb0bset favddrenb ; enable avddr voltage=3.8v call @wait_50ms ; delay 50ms for avddr voltage stabilize @ave_enable: xb0bset favenb ; enable ave+ voltage=3.0v/1.5v call @wait_50ms ; delay 50ms for ave+ voltage stabilize @pgia_init: mov a, #01110110b xb0mov ampm, a ; enable band gap, set :fds=?11? and pgia gain=200 mov a, #00000100b xb0mov ampcks, a ; set ampcks = ?100? for pgia working clock = 1.9k @ 4m x?tal mov a, #00h xb0mov ampchs, a ; selected pgia differential input channel= ai+, ai- @pgia_enable: xb0bset fampenb ; enable pgia function ? ; v (x+, x-) output = v (ai+, ai-) x 200 @adc_init: mov a, #00000110b xb0mov adcm, a ; selection adc reference voltage = v(r+, r-) mov a, #0236 xb0mov adcks, a ; set adcks = 236 for adc working clock = 100k @ 4m x?tal mov a, #00h xb0mov dfm, a ; set adc as continuous mode and wrs0 = ?0? @adc_enable: ; adc conversion rate =25 hz xb0bset fadcenb ; enable adc function @adc_wait: xb0bts1 fdrdy ; check adc output new data or not jmp @adc_wait ; wait for bit drdy = 1 @adc_read: ; output adc conversion word xb0bclr fdrdy xb0mov a, adcdh b0mov data_h_buf, a ; move adc c onversion high byte to data buffer. xb0mov a, adcdl b0mov data_l_buf, a ; move adc c onversion low byte to data buffer.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 93 version 1.6 ? ? ? note: please set adc relative registers first, than enable adc function bit. example: adc reference voltage changes: @adc_init: mov a, #00000110b xbmov adcm, a ; selection adc reference voltage = v(r+, r-) mov a, #0216 xb0mov adcks, a ; set adcks = 236 for adc working clock = 100k @ 4m x?tal mov a, #00h xb0mov dfm, a ; set adc as continuous mode and wrs0 = ?0? 25 hz @adc_enable: xb0bset fadcenb ; enable adc function @adc_wait: xb0bts1 fdrdy ; check adc output new data or not jmp @adc_wait ; wait for bit drdy = 1 @adc_read: ; output adc conversion word xb0bclr fdrdy xb0mov a, adcdh b0mov data_h_buf, a ; move adc c onversion high byte to data buffer. xb0mov a, adcdl b0mov data_l_buf, a ; move adc c onversion low byte to data buffer. ? ? @adc_rvs1: mov a, #00011011b ;don?t disable adc when change reference votlage xb0mov adcm, a ; selection adc reference voltage internal v(1.2v,0.4v) @@: xb0bts1 fdrdy ; check adc output new data or not jmp @b ; wait for bit drdy = 1 ; output adc conversion word xb0bclr fdrdy xb0mov a, adcdh b0mov data_h_buf, a ; move adc c onversion high byte to data buffer. xb0mov a, adcdl b0mov data_l_buf, a ; move adc c onversion low byte to data buffer. ? ? @adc_rvs2: mov a, #00011001b ;don?t disable adc when change reference votlage xbmov adcm, a ; selection adc as voltage measure. @@: xb0bts1 fdrdy ; check adc output new data or not jmp @b ; wait for bit drdy = 1 ; output adc conversion word xb0bclr fdrdy xb0mov a, adcdh b0mov data_h_buf, a ; move adc c onversion high byte to data buffer. xb0mov a, adcdl b0mov data_l_buf, a ; move adc c onversion low byte to data buffer. ?
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 94 version 1.6 10.5.6 lbtm : low battery detect register SN8P1917 provided two different way to measure power voltage. one is from adc reference voltage selection. it will be more precise but take more time and a little bit comp lex. the another way is using build in voltage comparator, divide power voltage and connect to p4.2, bit lbto will out put the p4.2 voltage higher or lower than acm(1.2v) 09ah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lbtm - - - - - lbto p41io lbtenb r/w - - - - - r r/w r/w after reset - - - - - 0 0 0 bit0 lbtenb: low battery detect mode control bit. 0 = disable low battery detect function, 1 = enable low battery detect function bit1: p41io: port 4.1 input/lbt function control bit. 0 = set p41 as input port, 1 = set p41 as lbt function bit2: lbto: low battery detect output bit. 0 = p4.2/lbt voltage higher than acm (1.2v) 1 = p4.2/lbt voltage lower than acm (1.2v) there are two circuit connections for lb t application, one is using p4.2 and p4.1, which can avoid power consumption in sleep mode, the another is using p4.2 only. the second way will leak a small current in power down mode but can use p4.1 for input application. these two circuits are following: lbtenb=1, p41io=1 lbtenb=1, p41io=0 p4.1 as lbt function, no leakage current in sleep mode p4.1 as input port, leak current in sleep mode. low battery voltage r1 r2 lbto=1 2.4v 1m 1m vdd<2.4v 3.6v 1.33m 0.66m vdd<3.6v 4.8v 1.5m 0.5m vdd<4.8v ? note: get lbto=1 more 10 times in a raw ever y certain period, ex. 20 ms or more to make sure the low battery signal is stable. comparator acm lbt vdd p4.2 p4.1 r1 r2 vss 0.1u comparator acm lbt vdd p4.2 r1 r2 vss 0.1u
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 95 version 1.6 10.5.7 analog setting and application the most applications of SN8P1917 were for dc measuremen t ex. weight scale, pressure measure. in different applications had each analog capacitor setting to avoi d vdd drop when charge pump enable or can save cost. following table indicate different applications setting wh ich mcu power source came from cr2032 battery, aa/aaa dry battery or external regulator capacitor table: ai+ ai- x+/x- r+/r- acm avddr ave+ avddcp c+/c- vdd (pin23) vdd (pin28) power type c ai+ c ai- c x c r c acm c avddr c ave+ c avddcp c c c avdd c dvdd cr2032 (2.4~3v) 0.1uf 0.1uf 0.01uf 0.1uf 1uf 1uf 2.2uf 10uf 1uf 10uf 0.1uf cr2032 ((4.4~6v)) 0.1uf 0.1uf 0.01uf 0.1uf 1uf 1uf 2.2uf no no 10uf 0.1uf aa/aaa bat.(2.4~3v) 0.1uf 0.1uf 0.01uf 0.1uf 1uf 1uf 4.7uf 10uf 1uf 10uf 0.1uf aa/aaa bat.(4.4~6v) 0.1uf 0.1uf 0.01uf 0.1uf 1uf 1uf 4.7uf no no 10uf 0.1uf external 5v reg. 0.1uf 0.1uf 0. 01uf 0.1uf 1uf 1uf 4.7uf no no 10uf 0.1uf ? note 1: when mcu source from cr2032battery, the ave+ loading can?t over 3ma, for example the load cell resistance can?t over 1k. ? note 2: in aa/aaa batter y application, the ave+ can loadin g 10ma current, so that the load cell can be up to 330 ohm. ? note 3: if vdd alwa y s over 4.2v, set char g e pump as auto or disable mode so that char g e pump will disable and current consumption will not time 2 from avddr and ave+. capacitors of avddr and c+/c- can be removed and connect avddcp to vdd . ? note 1:the positive note of c avddcp connect to avddcp and negative note connect to vdd ? note2: the positive note of c acm connect to avddr and negative note connect to acm
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 96 version 1.6 vdd=2.4v~4.2v analog capacitor connection vdd=4.2v~5.5v analog capacitor connection delay time: charge pump enable delay power type step 1 cpcks=#00001011b step 2 cpcks=#00000100b enable acm enable avddr enable ave+ cr2032 (2.4~3v) 200ms 100ms 5ms 50ms 50ms cr2032 ((4.4~6v)) - - 5ms 50ms 50ms aa/aaa bat.(2.4~3v) 100ms 50ms 5ms 50ms 50ms aa/aaa bat.(4.4~6v) - - 5ms 50ms 50ms external 5v reg. - - 5ms 50ms 50ms ? note 1: in cr2032 application, please set enou gh delay time or the vdd will drop when char g e pump enable ? note 2: if vdd always over 4.2v, set charge pump as auto or disable mode to disable charge pump. ? note 3: in aa/aaa dry battery application, de lay time is shorter than cr2032 application. avddcp c avddcp vdd acm c acm avddr c+ c- c c avddr ave+ c ave+ c avddr avss avddcp vdd acm c acm avddr c+ c- avddr ave+ c ave+ c avddr nc nc avss
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 97 version 1.6 1 1 1 1 1 1 application circuit 11.1 scale (load cell) application circuit ? note : please refer 10.5.7 for capacitor setting. c+ vdd (pin23) c- vss xin xout 3.58m x'tal p0.0 rst p1.0 10k 104 p4.0 p1.1 vss 20pf 20pf avddr r- r+ x - x+ ai- ai+ bridge type sensor ave+ com 3 seg 0 lcd com 2 ave+ p4.1 p4.2 p1.2 com 1 com 0 seg 1 seg 11 seg 10 ....................................... vlcd vdd/avvddr ave+ p5.0 p5.1 p5.2 c ai+ 100 c ai- c x c r+ c r- c ave+ c avddr c avdd c c vdd (pin28) c dvdd avddcp avss acm avddr c acm vdd
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 98 version 1.6 11.2 thermometer application circuit ? note : please refer 10.5.7 for capacitor setting. c+ vdd (pin23) c- vss xin xout 3.58m x'tal p0.0 rst p1.0 10k 104 p4.0 p1.1 vss 20pf 20pf avddr r- r+ x - x+ com 3 seg 0 lcd com 2 ave+ p4.1 p4.2 p1.2 com 1 com 0 seg 1 seg 11 seg 10 ....................................... vlcd vdd/avvddr ave+ p5.0 p5.1 p5.2 100 c x c r+ c r- c ave+ c avddr c avdd c c vdd (pin28) c dvdd ai- ai+ thermopile ave+ thermistor acm acm 0.1uf 0.1uf avddcp avss acm c acm c avddcp vdd avddr
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 99 version 1.6 1 1 1 2 2 2 instruction set table field mnemonic description c dc z cycle mov a,m a m - - 1 m mov m,a m a - - - 1 o b0mov a,m a m (bank 0) - - 1 v b0mov m,a m (bank 0) a - - - 1 e mov a,i a i - - - 1 b0mov m,i m i, m = only supports 0x80~0x87, (e.g. r, y, z , rbank ,pflag??.) - - - 1 xch a,m a m - - - 1 b0xch a,m a m (bank 0) - - - 1 movc r, a rom [y,z] - - - 2 adc a,m a a + m + c, if occur carry, then c=1, else c=0 1 a adc m,a m a + m + c, if occur carry, then c=1, else c=0 1 r add a,m a a + m, if occur carry, then c=1, else c=0 1 i add m,a m a + m, if occur carry, then c=1, else c=0 1 t b0add m,a m (bank 0) m (bank 0) + a, if occur carry, then c=1, else c=0 1 h add a,i a a + i, if occur carry, then c=1, else c=0 1 m sbc a,m a a - m - /c, if occur borrow, then c=0, else c=1 1 e sbc m,a m a - m - /c, if occur borrow, then c=0, else c=1 1 t sub a,m a a - m, if occur borrow, then c=0, else c=1 1 i sub m,a m a - m, if occur borrow, then c=0, else c=1 1 c sub a,i a a - i, if occur borrow, then c=0, else c=1 1 daa to adjust acc?s data format from hex to dec. - - 1 and a,m a a and m - - 1 l and m,a m a and m - - 1 o and a,i a a and i - - 1 g or a,m a a or m - - 1 i or m,a m a or m - - 1 c or a,i a a or i - - 1 xor a,m a a xor m - - 1 xor m,a m a xor m - - 1 xor a,i a a xor i - - 1 swap m a (b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 p swapm m m(b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 r rrc m a rrc m - - 1 o rrcm m m rrc m - - 1 c rlc m a rlc m - - 1 e rlcm m m rlc m - - 1 s clr m m 0 - - - 1 s bclr m.b m.b 0 - - - 1 bset m.b m.b 1 - - - 1 b0bclr m.b m(bank 0).b 0 - - - 1 b0bset m.b m(bank 0).b 1 - - - 1 cmprs a,i zf,c a - i, if a = i, then skip next instruction - 1 + s b cmprs a,m zf,c a ? m, if a = m, then skip next instruction - 1 + s r incs m a m + 1, if a = 0, then skip next instruction - - - 1 + s a incms m m m + 1, if m = 0, then skip next instruction - - - 1 + s n decs m a m - 1, if a = 0, then skip next instruction - - - 1 + s c decms m m m - 1, if m = 0, then skip next instruction - - - 1 + s h bts0 m.b if m.b = 0, then skip next instruction - - - 1 + s bts1 m.b if m.b = 1, then skip next instruction - - - 1 + s b0bts0 m.b if m (bank 0).b = 0, then skip next instruction - - - 1 + s b0bts1 m.b if m (bank 0).b = 1, then skip next instruction - - - 1 + s jmp d pc15/14 rompages1/0, pc13~pc0 d - - - 2 call d stack pc15~pc0, pc15/14 rompages1/0, pc13~pc0 d - - - 2 m ret pc stack - - - 2 i reti pc stack, and to enable global interrupt - - - 2 s nop no operation - - - 1 c
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 100 version 1.6 1 1 1 3 3 3 development tools 13.1 development tool version 13.1.1 ice (in circuit emulation) z sn8ice 1k: (s8kd-2) full function emulates SN8P1917 series ? sn8ice1k ice emulation notice ? operation voltage of ice: 3.0v~5.0v. ? recommend maximum emulation speed at 5v: 4 mips (e.g. 16mhz crystal and fcpu = fhosc/4). ? use SN8P1917 ev-kit to emulation analog function. ? note: s8ice2k doesn?t support SN8P1917 serial emulation. 13.1.2 otp writer z easy writer v1.0: otp programming is controlled by ice wit hout firmware upgrade suffers. please refer easy writer user manual for detailed information. z mp-ez writer v1.0: stand-alone operation to support SN8P1917 mass production ? note: writer 3.0 doesn?t support SN8P1917 otp programming. 13.1.3 ide (integrated development environment) sonix 8-bit mcu integrated development environment include assembler, ice debugger and otp writer software. z for sn8ice 1k: sn8ide 1.99v or later z for easy writer and mp-easy writer: sn8ide 1.99w or later z m2ide v1.0x doesn?t support SN8P1917.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 101 version 1.6 13.2 otp programming pin to transition board mapping 13.2.1 the pin assignment of easy and mp ez writer transition board socket: easy writer jp1/jp2 easy writer jp3 (mapping to 48-pin text tool) vss 2 1 vdd dip1 1 48 dip48 ce 4 3 clk/pgclk dip2 2 47 dip47 oe/shiftdat 6 5 pgm/otpclk dip3 3 46 dip46 d0 8 7 d1 dip4 4 45 dip45 d2 10 9 d3 dip5 5 44 dip44 d4 12 11 d5 dip6 6 43 dip43 d6 14 13 d7 dip7 7 42 dip42 vpp 16 15 vdd dip8 8 41 dip41 rst 18 17 hls dip9 9 40 dip40 alsb/pdb 20 19 - dip10 10 39 dip39 dip11 11 38 dip38 jp1 for mp transition board dip12 12 37 dip38 jp2 for writer v3.0 transition board dip13 13 36 dip36 dip14 14 35 dip35 dip15 15 34 dip34 dip16 16 33 dip33 dip17 17 32 dip32 dip18 18 31 dip31 dip19 19 30 dip30 dip20 20 29 dip29 dip21 21 28 dip28 dip22 22 27 dip27 dip23 23 26 dip26 dip24 24 25 dip25 jp3 for mp transition board 13.2.2 the pin assignment of writer v3.0 transition board socket: gnd 2 1 vdd ce 4 3 clk oe 6 5 pgm d0 8 7 d1 d2 10 9 d3 d4 12 11 d5 d6 14 13 d7 vpp 16 15 vdd rst 18 17 hls 20 19 writer v3.0 jp1 pin assignment
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 102 version 1.6 13.2.3 SN8P1917 series programming pin mapping: otp programming pin of SN8P1917 series chip name SN8P1917 easy, mp-ez writer and writer v3.0 otp ic / jp3 pin assignment number pin number pin 1 vdd 10,23,28 vdd 2 gnd 17,25,40 vss 3 clk 30 p1.0 4 ce - - 5 pgm 31 p1.1 6 oe 32 p1.2 7 d1 - - 8 d0 - - 9 d3 - - 10 d2 - - 11 d5 - - 12 d4 - - 13 d7 - - 14 d6 - - 15 vdd 10,23,28 vdd 16 vpp 41 rst 17 hls - - 18 rst - - 19 - - - 20 alsb/pdb 33 p1.3
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 103 version 1.6 1 1 1 4 4 4 electrical characteristic 14.1 absolute maximum rating supply voltage (v dd )??????????????..????????????? - 0.3v ~ 6.0v input in voltage (v in )???????????..???.???????? v ss - 0.2v ~ v dd + 0.2v operating ambient temperature (t opr )??????????????????? 0 c ~ + 70 c storage ambient temperature (t stor )???????..???.???????? ?40 c ~ + 125 c 14.2 electrical characteristic (all of voltages refer to v ss , v dd = 5.0v,f osc = 4mhz,fcpu=1mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit operating voltage v dd normal mode, v pp = v dd 2.4 5.0 5.5 v ram data retention voltage v dr 1.5 - v v dd rise rate v por v dd rise rate to ensure power-on reset 0.05 - - v/ms vil1 all input ports vss - 0.3vdd v input low voltage vil2 reset pin vss - 0.2vdd v vih1 all input ports 0.7vdd - vdd v input high voltage vih2 reset pin 0.9vdd - vdd v reset pin leakage current i lekg v in = v dd - - 2 ua v in = v ss , v dd = 3v 100 200 300 k ? i/o port pull-up resistor r up v in = v ss , v dd = 5v 50 100 180 k ? i/o port input leakage current i lekg pull-up resistor disable, v in = v dd - - 2 ua i/o output source current i o h v op = v dd - 0.5v 8 12 - ma sink current i o l v op = v ss + 0.5v 8 15 - ma int n trigger pulse width t int 0 int0 ~ int1 interrupt request pulse width 2/f cpu - - cycle vdd= 5v 4mhz crystal - 1.5 3 ma idd1 normal mode (low power disable, analog parts off) vdd= 3v 4mhz crystal - 0.5 1 ma vdd= 5v 4mhz crystal - 0.9 1.8 ma idd2 normal mode (low power enable analog parts off) vdd= 3v 4mhz crystal - 0.35 0.7 ma vdd= 5v 4mhz crystal - 2.5 5 ma idd3 normal mode (low power disable analog parts on) vdd= 3v 4mhz crystal - 2.2 4.4 ma vdd= 5v 4mhz crystal - 2 4 ma idd4 normal mode (low power enable analog parts on) vdd= 3v 4mhz crystal - 1.5 3 ma vdd= 5v ihrc - 1.7 3.4 ma idd5 normal mode (low power disable, analog parts off) vdd= 3v ihrc - 0.9 1.8 ma vdd= 5v ihrc - 1.1 2.2 ma idd6 normal mode (low power enable analog parts off) vdd= 3v ihrc - 0.7 1.4 ma vdd= 5v ihrc - 2.5 5 ma supply current idd7 normal mode (low power disable analog parts on) vdd= 3v ihrc - 2.2 4.4 ma
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 104 version 1.6 vdd= 5v ihrc - 2.1 4.2 ma idd8 normal mode (low power enable analog parts on) vdd= 3v ihrc - 1.9 3.8 ma vdd= 5v ilrc 32khz - 10 20 ua idd9 slow mode (stop high clock, lcd off, cpr off) vdd= 3v ilrc 16khz - 3 6 ua vdd= 5v ilrc 32khz - 25 50 ua idd10 slow mode (stop high clock, lcd on, cpr off) vdd= 3v ilrc 16khz - 12 24 ua vdd= 5v ilrc 32khz - 300 600 ua idd11 slow mode (stop high clock, lcd on, cpr on) vdd= 3v ilrc 16khz - 250 500 ua vdd= 5v - 1 2 ua supply current idd12 sleep mode vdd= 3v - 0.7 1.5 ua internal high clock freq. f ihrc internal high rc oscillator frequency (fcpu= f ihrc /16) 14 16 18 mhz lvd detect level v lvd internal por detect level 1.7 2.0 2.3 v ? note: analog parts including charge pu mp regulator (cpr), pgia and adc.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 105 version 1.6 (all of voltages refer to vdd=3.8v f osc = 4mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit analog to digital converter operating current i dd_adc run mode @ 3.8v 800 1000 ua power down current i pdn stop mode @ 3.8v 0.1 1 a conversion rate f smp adcks: 200khz 25 sps r+, r- input range (external ref.) 0.4 2.0 v reference voltage input voltage vref r+, r- input range (internal ref.) 0.2 2.0 v differential non-linearity dnl adc range 28125 0.5 0.5 lsb integral non-linearity inl adc range 28125 1 4 lsb no missing code nmc adc range 28125 16 bit noise free code nfc adc range 28125 14 16 bit effective number of bits enob adc range 28125 14 16 bit adc input range v ain 0.4 2.0 v temperature sensor inaccuracy e ts inaccuracy range vs. real temp. 8 pgia current consumption i dd_pgia run mode @ 3.8v 300 500 ua power down current i pdn stop mode @ 3.8v 0.1 a input offset voltage vos 25 50 uv bandwidth bw 100 hz pgia gain range (gain=200x) gr vdd = 3.8v 180 200 250 pgia input range vopin vdd = 3.8v 0.4 2 v pgia output range vopout vdd = 3.8v 0.4 2 v band gap reference (refer to acm) band gap reference voltage v bg 1.160 1.210 1.270 v reference voltage temperature coefficient t acm 50* ppm/ operating current i bg run mode @ 3.8v 50 100 ua charge pump regulator supply voltage v cps normal mode 2.4 5.5 v regulator output voltage avddr v avddr 3.5 3.75 4.1 v regulator output voltage ave+ v ave+ ave+ set as 3.0v 2.8 3.0 3.3 v analog common voltage v acm 1.15 1.21 1.27 v regulator output current capacity i va+ 10 ma quiescent current i qi 700 1400 ua v acm driving capacity i src 10 - - a v acm sinking capacity i snk 1 - - ma ? note : when char g e pump enable, current consumption will be time 2 of adc, pgia, cpr and loadin g from ave+, avddr.
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 106 version 1.6 1 1 1 5 5 5 package information 15.1 ssop 48 pin min nor max min nor max symbols (inch) (mm) a 0.095 0.102 0.110 2.413 2.591 2.794 a1 0.008 0.012 0.016 0.203 0.305 0.406 a2 0.089 0.094 0.099 2.261 2.388 2.515 b 0.008 0.010 0.030 0.203 0.254 0.762 c - 0.008 - - 0.203 - d 0.620 0.625 0.630 15.748 15.875 16.002 e 0.291 0.295 0.299 7.391 7.493 7.595 [e] - 0.025 - - 0.635 - he 0.396 0.406 0.416 10.058 10.312 10.566 l 0.020 0.030 0.040 0.508 0.762 1.016 l1 - 0.056 - - 1.422 - y - - 0.003 - - 0.076 0 - 8 0 - 8
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 107 version 1.6 1 1 1 6 6 6 marking definition 16.1 introduction there are many different types in sonix 8-bit mcu production line. this note listed the produ ction definition of all 8-bit mcu for order or obtain information. this definition is only for blank otp mcu. 16.2 marking indetification system sn8 x part no. x x x title sonix 8-bit mcu production rom type p=otp material b = pb-free package g = green package temperature range - = 0 ~ 70 shipping package w = wafer h = dice p = p-dip x = ssop device 1917
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 108 version 1.6 16.3 marking example name rom type device package temperature material SN8P1917pb otp 1917 p-dip 0 ~70 pb-free package SN8P1917pg otp 1917 p-dip 0 ~70 green package 16.4 datecode system x x x x xxxxx year month 1=january 2=february . . . . 9=september a=october b=november c=december sonix internal use day 1=01 2=02 . . . . 9=09 a=10 b=11 . . . . 03= 2003 04= 2004 05= 2005 06= 2006 . . . .
SN8P1917 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 109 version 1.6 sonix reserves the right to make change without further notic e to any products herein to im prove reliability, function or design. sonix does not assume any liability arising out of th e application or use of any product or circuit described herein; neither does it convey any license under its patent rights no r the rights of others. sonix products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other applicati on in which the failure of the sonix product could create a situation where personal injury or death may occur. s hould buyer purchase or use sonix products for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cos t, damages, and expenses, and reasonabl e attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 9f, no. 8, hsien cheng 5th st, chupei city, hsinchu, taiwan r.o.c. tel: 886-3-551 0520 fax: 886-3-551 0523 taipei office: address: 15f-2, no. 171, song ted road, taipei, taiwan r.o.c. tel: 886-2-2759 1980 fax: 886-2-2759 8180 hong kong office: address: flat 3 9/f energy plaza 92 granville road, tsimshatsui east kowloon. tel: 852-2723 8086 fax: 852-2723 9179 technical support by email: sn8fae@sonix.com.tw

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